Systems Power Integrity Engineer

Location: Cupertino, CA Fully Onsite

Introduction

The Mac organization is seeking an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis, and validation aspects of Mac and Accessory products development. This role requires deep knowledge and familiarity with power delivery network design, analysis, and validation methods. The successful candidate will work with multi-functional teams to design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements.

Required Skills & Qualifications

• M.S Degree with 4~7 years relevant work experience.
• Proven technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices, and trade-offs for PDN design and optimization.
• Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex) is required.
• Relevant proven understanding of HSPICE, Spectre, AMS, and Simplis models for system-level transient droop analysis is also vital.
• Understanding of die-package-board power delivery network co-design constraints and tradeoffs.
• Ability to work with multiple cross-functional teams to make the right trade-offs on the system performance is a must.
• Prior work experience at client or in client's Industry.

Applicants must be able to work directly for Artech on W2.

Preferred Skills & Qualifications

• Ph. D with minimum 3-4 year’s experience.
• Good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration care-about.
• Deep experience in CPM (Chip-Power-Model) usage for system transient analysis is an added benefit.
• Hands-on experiences on package or board layout with Cadence is a plus. The candidate with this skill is expected to perform proof of concept layout study with Cadence.
• Experience with Python, MATLAB or other programming languages is desired.
• Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.

Day-to-Day Responsibilities

• Conduct pathfinding studies in silicon development phase and provide feedback to silicon and packaging teams on system integration tradeoffs.
• Complete target impedance analysis, transient voltage droop, and phase margin/stability analysis.
• Guide and work closely with the system team on component selections for optimum power solutions.
• Work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase.
• Collaborate with HW Validation teams to develop test-suites for system-level validation and evaluation of design margins on the power domains.
• Provide PI support throughout the product design process, including system pathfinding, verification stages, and characterization reviews with continuing guidance through production and ramp.

Company Benefits & Culture

• Comprehensive health, dental, and vision insurance.
• Generous paid time off and holiday schedule.
• Opportunities for professional development and career growth.

For immediate consideration please click APPLY to begin the screening process with Alex.