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Staff ASIC Design Engineer

Parade Technologies Ltd

  • Beaverton, OR
  • 8 days ago
  • $150,000–$180,000 Per Year

Highlights

Annual base salary 150000 - 180000 Responsibilities SOC subsystem architect including documentation of micro-architectureLead design team for major subsystems of large SOCs Qualifications BSMS degree with 10 years of relevant work experienceExpert understanding of digital design and verification practicesAbility to write RTL based on a specification and simulate vectors to verify RTLExperience using System Verilog SV and at least two prior RTL designsExtensive knowledge of PCIe USB3 or Power Delivery Required Experience Demonstrate an expert knowledge of System Verilog SV or similar verification languageDemonstrate an expert knowledge of Verilog for chip design and verificationUnderstanding the ASIC flow from MAS to silicon including RTL design verification synthesis timing constraints GLS FPGA prototyping and first silicon bring up and debugExperience with high-speed serial protocols USB3 PCIe Ethernet etc. Experience with creating module level test benches and BFMs.

Numbers & Facts

LocationBeaverton, OR
Salary$150,000–$180,000 Per Year

Description

Annual base salary 150000 - 180000 Responsibilities SOC subsystem architect including documentation of micro-architectureLead design team for major subsystems of large SOCs Qualifications BSMS degree with 10 years of relevant work experienceExpert understanding of digital design and verification practicesAbility to write RTL based on a specification and simulate vectors to verify RTLExperience using System Verilog SV and at least two prior RTL designsExtensive knowledge of PCIe USB3 or Power Delivery Required Experience Demonstrate an expert knowledge of System Verilog SV or similar verification languageDemonstrate an expert knowledge of Verilog for chip design and verificationUnderstanding the ASIC flow from MAS to silicon including RTL design verification synthesis timing constraints GLS FPGA prototyping and first silicon bring up and debugExperience with high-speed serial protocols USB3 PCIe Ethernet etc.Experience with creating module level test benches and BFMs

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