Sr. Manager, Foundation IP (Standard Cells & Memories),, Annapurna Labs

Annapurna Labs, our silicon organization within AWS Utility Computing, builds the custom chips behind AWS - Graviton, Nitro, Inferentia and Trainium. Our Machine Learning Acceleration (MLA) team develops the Trainium and Inferentia SoCs that train and serve frontier AI models at datacenter scale.

On AI silicon, foundation IP is not a commodity. SRAM and register files dominate die area and power, and every picosecond and square micron in a standard cell library compounds across billions of instances. We are looking for a Sr. Manager, Foundation IP to own that layer end to end - from foundry DTCO and vendor roadmaps, through custom cell and memory definition, to characterization and silicon correlation on leading-edge GAA nodes (N3, N2 and below).

You will be the single technical point of contact for our foundation IP vendors and memory providers, lead a hands-on team of 3-6 engineers, and partner with Architecture, Physical Design, CAD, DFT and Product Engineering to turn IP decisions into measurable PPA wins on every Trainium and Inferentia generation. This is a player-coach role: you will set strategy and hold vendors to Amazon's bar - and you will also review schematics, layouts and Liberty data yourself.

Key job responsibilities

• Foundation IP strategy & vendor ownership

• Own the foundation IP roadmap - standard cell libraries, memory compilers, custom macros, GPIO/ESD, eFuse/OTP and PVT sensors - aligned to multi-generation Trainium and Inferentia product plans.

• Serve as the primary technical interface to foundation IP vendors and the foundry: define deliverable specifications, negotiate SOWs and schedules, and drive ECOs, version control and release cadence.

• Influence vendor roadmaps to secure features and PPA that differentiate AWS silicon; resolve quality escapes with data, not escalation alone.

• Build IP intake and QA mechanisms - checklists, regressions and acceptance criteria for every library, memory and view drop.

• PPA evaluation & library selection

• Lead quantitative evaluation of competing libraries, memory compilers and cell architectures using block-level synthesis and place-and-route benchmarks (Synopsys Fusion Compiler, Cadence Innovus) on representative ML datapath, SRAM-heavy and high-utilization blocks.

• Drive cell-architecture decisions - cell height, mixed-height (short/tall) libraries, VT and channel-length flavors, nanosheet width options, backside power delivery - with clear PPA, cost and schedule tradeoffs.

• Partner with Physical Design and CAD to deploy selected IP into the RTL-to-GDSII flow and close the loop on post-implementation PPA.

• Memory specification & vendor interface

• Define memory requirements for ML accelerator workloads - single/dual-port SRAM, multi-port register files, ROM, TCAM/CAM - including capacity, banking, bandwidth, latency, Vmin and leakage targets.

• Specify bitcell selection (high-density vs. high-current), read/write assist, redundancy and repair, MBIST/BISR interfaces, power-gating, retention and sleep modes.

• Own the memory vendor relationship, compiler release qualification, and integration support for Physical Design and DFT teams.

• Latch arrays & custom memory macros

• Lead design and integration of latch-based arrays and custom register files for small, high-bandwidth buffers where compiler SRAM or flop arrays fall short on PPA.

• Define the selection methodology across compiler SRAM, custom macros, latch arrays and flop-based storage; own the timing, DFT and characterization strategy for latch-based structures.

• Drive custom macro development (multi-port register files, TCAM/CAM) from specification through layout, characterization and silicon validation.

• Custom & combo standard cells

• Mine synthesized ML netlists and cell-usage statistics to find custom cell opportunities - combo/complex cells, multi-bit flops, datapath compressors and MAC-optimized cells, ganged buffers, clock and power-management cells.

• Write cell specifications and work hands-on with circuit and layout engineers on topology, sizing, pin access, routability and DFM.

• Take custom cells through characterization, view generation, QA and PnR enablement, and quantify the block-level PPA benefit.

• Characterization & signoff views

• Own characterization strategy and quality for all foundation IP: Liberty (NLDM, CCS, ECSM), LVF/POCV, CCS noise and power, EM limits, LEF/abstracts and Verilog models.

• Set PVT corner strategy, including low-voltage and overdrive corners, with Physical Design, signoff and Product Engineering.

• Drive characterization flows (Synopsys PrimeLib/SiliconSmart, Cadence Liberate) and view QA (e.g., Siemens Solido Crosscheck), with SPICE correlation in Synopsys PrimeSim/HSPICE and Cadence Spectre.

• Foundry DTCO & node enablement

• Engage the foundry from early PDK versions on DTCO, cell architecture, design rules and device options for N3, N2 and below nodes.

• Work with others to define silicon characterization plans for libraries and memories (Vmin, speed, leakage, aging, self-heating) and correlate silicon to models, on both testchips and/or products.

• Track device and reliability model updates across PDK revisions and assess their impact on IP and product PPA.

• Team leadership

• Hire, develop and lead a small team to deliver on the above; set technical direction, review designs, and raise the bar on quality and execution.

• Report IP health, risks and PPA metrics to senior leadership through clear, data-driven narratives and decision documents.