Silicon Engineering Manager

Silicon Engineering Manager (Accenture LLP; Scottsdale, AZ): Accenture LLP has multiple openings for the position of Silicon Engineering Manager in Scottsdale, AZ, and the job duties are as follows:

• Contribute to the development of Gate Level Simulation (GLS) TestBench architecture and verification of ASIC design with provided Netlist by developing or enhancing TestBench, running simulation of testcase suites and debugging failures.
• Drive the definition of TestPlan for RTL design through design specification.
• Define, develop, and integrate testcases to successfully verify RTL design using SV/UVM/C/Python languages and methodology.
• Work closely with design and architect engineers to define, develop and integrate required TestBench developments required for the RTL functional verification.
• Define, develop, and integrate functional coverage in the TestBench following Coverage Driven Verification methodology.
• Contribute development of testcases in C language to verify CPU based transactions as per the TestPlan.
• Define, develop, and integrate random constraints that will generate random valid input stimulus during daily testcase regressions.
• Supervise team execution and collaborate with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements in timely manner.