| Location | Sunnyvale, CA |
| Salary | $50–$65 Per Hour |
Role: SI/PI Engineer
Location: Sunnyvale CA (Onsite only)
Job Description:
Role Summary
We are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.
Team: Hardware Design Engineering Advanced Packaging
Key Responsibilities
Perform SI/PI analysis and design optimization for advanced silicon packages (CoWoS, EMIB, chiplet-based architectures, fan-out wafer-level packaging)
Develop and validate high-speed channel models for package interconnects including bumps, microbumps, TSVs, RDL layers, and silicon/organic interposers
Conduct full-wave electromagnetic (EM) simulations of package structures to characterize S-parameters, crosstalk, impedance, and insertion/return loss
Design and optimize Power Distribution Networks (PDN) including decoupling strategy, IR drop analysis, and AC impedance profiling from die to board
Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps)
Collaborate with IC design, package substrate design, PCB layout, and thermal/mechanical teams to co-optimize package electrical performance
Develop and correlate simulation models with lab measurements (VNA, TDR, oscilloscope, power noise measurements)
Define SI/PI design guidelines and constraints for package substrate stackup, routing rules, and bump/via assignments
Support design-for-manufacturability (DFM) reviews with OSAT partners and substrate vendors
Investigate and resolve SI/PI-related failures during silicon bring-up and validation phases
Required Qualifications
5+ years of experience in SI/PI analysis for semiconductor packaging or high-speed PCB design
Strong proficiency with industry-standard EM and circuit simulation tools:
Deep understanding of transmission line theory, Maxwell's equations, and S-parameter analysis
Experience with high-speed interface protocols (PCIe, UCIe, HBM, DDR, Ethernet SerDes)
Proficiency in package stackup design, impedance control, and via transition optimization
Hands-on experience with measurement correlation (VNA, TDR/TDT, near-field scanning)
Programming/scripting skills (Python, MATLAB, Tcl) for automation and post-processing
Preferred Qualifications
Experience with 2.5D/3D advanced packaging technologies (CoWoS, EMIB, Foveros, hybrid bonding)
Familiarity with chiplet-based disaggregated architectures and die-to-die interconnect standards (UCIe, BoW)
Knowledge of co-simulation methodologies (chip-package-board co-design)
Experience with statistical analysis and Monte Carlo methods for manufacturing variation impact
Understanding of thermal-aware electrical analysis (electro-thermal co-simulation)
Contributions to IEEE/DesignCon publications or industry standards committees (JEDEC, OIF, UCIe Consortium)
Experience working with OSATs (ASE, Amkor, TSMC InFO/CoWoS) and substrate vendors
Notes:- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits: Danta offers a compensation package to all W2 employees that are competitive in the industry. It consists of competitive pay, the option to elect healthcare insurance (Dental, Medical, Vision), Major holidays and Paid sick leave as per state law.
The rate/ Salary range is dependent on numerous factors including Qualification, Experience and Location.