Senior Technical Lead - Silicon Platform Validation, Python

Job Description

Senior Technical Lead - Silicon Platform Validation, Python

Others, Others

Job Summary

We are seeking a highly motivated FCBGA Package Layout Engineer with expertise in advanced semiconductor package design and substrate layout development. The ideal candidate will be responsible for the complete package layout cycle, including bump map development, substrate routing, signal integrity considerations, manufacturability reviews, and collaboration with foundries, OSATs, substrate vendors, and cross-functional design teams. Key Responsibilities • Develop and maintain FCBGA package substrate layouts for high-performance computing, networking, AI, and ASIC products. • Create and optimize: o Die bump maps o Ball maps o Escape routing strategies o Power and ground distribution networks o RDL and substrate stack-ups • Perform package floorplanning and routing using industry-standard EDA tools. • Work closely with: o Silicon design teams o Signal Integrity (SI) engineers o Power Integrity (PI) engineers o PCB design teams o Assembly and manufacturing partners • Generate package documentation including: o Substrate drawings o Manufacturing deliverables Classification: Internal o Design rule specifications o Gerber/ODB++ outputs • Conduct layout reviews and design signoffs. • Drive package optimization for: o Routability o Cost o Yield o Reliability o Electrical performance • Support package qualification activities and failure analysis investigations. • Interface with OSATs and substrate suppliers to resolve design and manufacturing issues. • Ensure compliance with package design rules and customer requirements. Required Qualifications • Bachelors or Masters degree in: o Electronics Engineering o Electrical Engineering o Semiconductor Engineering o Related field • 5+ years of experience in semiconductor package design and layout. • Strong understanding of: o Flip-Chip BGA (FCBGA) o Wirebond packages o High-density substrate technologies o Package assembly processes Classification: Internal • Experience with: o Cadence Allegro Package Designer Plus (APD/APD+) o Cadence SiP Layout o Xpedition Package Designer (preferred) o AutoCAD (optional) • Knowledge of: o Signal Integrity (SI) o Power Integrity (PI) o Thermal considerations o EM/IR analysis fundamentals • Familiarity with substrate technologies: o ABF substrates o Build-up layers o Coreless substrates o HDI structures Preferred Skills • Experience with advanced packaging technologies: o 2.5D Interposer o CoWoS o EMIB o HBM integration o Chiplet-based architectures • Understanding of: o DDR, PCIe, UCIe, Ethernet interfaces o High-speed SerDes routing o JEDEC packaging standards Classification: Internal • Ability to develop package stack-ups and routing strategies for large body FCBGA packages (>50mm). • Experience working directly with TSMC, Intel, Samsung, ASE, Amkor, SPIL, or other OSAT/substrate suppliers. Key Technical Skills • Bump map planning and optimization • Ball map design • Escape routing • Package floorplanning • Substrate stack-up definition • Power delivery network (PDN) design • Design rule checking (DRC) • LVS verification • SI/PI awareness • Manufacturing and assembly knowledge • Package reliability considerations Desired Soft Skills • Strong analytical and problem-solving skills • Excellent communication and presentation abilities • Ability to lead package design reviews • Cross-functional collaboration skills • Customer-facing technical communication experience • Ability to manage multiple projects simultaneously Nice-to-Have Experience • AI accelerator packages • HPC processors • Networking ASICs Classification: Internal • Data center products • Chiplet packaging architectures • FCBGA packages with >5,000 signals and >10,000 substrate nets • Advanced packaging programs involving TSMC CoWoS, InFO, or Intel EMIB technologies

Key Responsibilities

Develop and maintain FCBGA package substrate layouts for high-performance computing, networking, AI, and ASIC products. • Create and optimize: o Die bump maps o Ball maps o Escape routing strategies o Power and ground distribution networks o RDL and substrate stack-ups • Perform package floorplanning and routing using industry-standard EDA tools. • Work closely with: o Silicon design teams o Signal Integrity (SI) engineers o Power Integrity (PI) engineers o PCB design teams o Assembly and manufacturing partners • Generate package documentation including: o Substrate drawings o Manufacturing deliverables Classification: Internal o Design rule specifications o Gerber/ODB++ outputs • Conduct layout reviews and design signoffs. • Drive package optimization for: o Routability o Cost o Yield o Reliability o Electrical performance • Support package qualification activities and failure analysis investigations. • Interface with OSATs and substrate suppliers to resolve design and manufacturing issues. • Ensure compliance with package design rules and customer requirements.

Skill Requirements

Key Technical Skills • Bump map planning and optimization • Ball map design • Escape routing • Package floorplanning • Substrate stack-up definition • Power delivery network (PDN) design • Design rule checking (DRC) • LVS verification • SI/PI awareness • Manufacturing and assembly knowledge • Package reliability considerations

Other Requirements

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Information at a Glance

Why HCLTech?

At HCLTech, youll supercharge your potential. Youll find your career. And youll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 230,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion.