Senior Technical Architect

Job Description

Senior Technical Architect

Bangalore, Karnataka

Job Summary

JD for PD:

Perform end‑to‑end physical design flow:

Floorplanning

Power planning (PG grid, IR)

Placement & optimization

CTS (Clock Tree Synthesis)

Routing

Post‑route optimization

Achieve timing closure across all modes and corners

Resolve DRC, LVS, ERC and signoff violations

Handle low‑power design techniques:

Multi‑Vt, Multi‑voltage (UPF)

Power gating, clock gating

Perform physical verification and signoff:

STA (Primetime)

SI / Crosstalk

IR drop & EM analysis

Work on advanced nodes (7nm, 5nm, 3nm or below)

Collaborate with:

RTL & Micro‑architecture teams

DFT & Test engineers

Foundry and CAD teams

Debug complex timing, congestion, power, and variability issues

Drive methodology improvements and automation (scripts/flows).

JD for STA:

Experience: 5+ years

Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)

Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV

Analyze and resolve timing violations across hierarchical boundaries

Constraint Management

Define and validate SDC constraints for chip-level integration

Ensure proper timing budgeting and partitioning across blocks

Review and align block-level constraints with chip-level requirements

Signoff & Methodology

Lead signoff STA using tools like:

Synopsys PrimeTime

Cadence Tempus

Implement and improve:

MCMM (Multi-Corner Multi-Mode) flows

SI-aware analysis (crosstalk, noise)

ECO strategies for timing closure

Ensure timing correlation between block and top level

Debug & Optimization

Perform deep analysis on:

Critical paths

False/multicycle paths

Clock domain crossings (CDC timing perspective)

Drive timing ECOs with minimal impact on power/area

Strong expertise in:

STA fundamentals (setup/hold, skew, jitter, latency)

OCV/AOCV/POCV concepts

SI effects and derates

Hands-on experience with:

Synopsys PrimeTime / Cadence Tempus

Deep understanding of:

Clock tree design and analysis

Low power (UPF/CPF) impact on timing

Advanced nodes (7nm, 5nm preferred)

Experience in hierarchical STA flows

Exposure to automation (TCL/Python scripting)

Knowledge of EM/IR and physical effects on timing

Experience working with global teams / customers

Zero/near-zero timing violations at tapeout

Clean signoff across all modes/corners

Predictable timing closure cycles

Strong correlation between block and top-level timing

Key Responsibilities

JD for PD:

Perform end‑to‑end physical design flow:

Floorplanning

Power planning (PG grid, IR)

Placement & optimization

CTS (Clock Tree Synthesis)

Routing

Post‑route optimization

Achieve timing closure across all modes and corners

Resolve DRC, LVS, ERC and signoff violations

Handle low‑power design techniques:

Multi‑Vt, Multi‑voltage (UPF)

Power gating, clock gating

Perform physical verification and signoff:

STA (Primetime)

SI / Crosstalk

IR drop & EM analysis

Work on advanced nodes (7nm, 5nm, 3nm or below)

Collaborate with:

RTL & Micro‑architecture teams

DFT & Test engineers

Foundry and CAD teams

Debug complex timing, congestion, power, and variability issues

Drive methodology improvements and automation (scripts/flows).

JD for STA:

Experience: 5+ years

Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)

Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV

Analyze and resolve timing violations across hierarchical boundaries

Constraint Management

Define and validate SDC constraints for chip-level integration

Ensure proper timing budgeting and partitioning across blocks

Review and align block-level constraints with chip-level requirements

Signoff & Methodology

Lead signoff STA using tools like:

Synopsys PrimeTime

Cadence Tempus

Implement and improve:

MCMM (Multi-Corner Multi-Mode) flows

SI-aware analysis (crosstalk, noise)

ECO strategies for timing closure

Ensure timing correlation between block and top level

Debug & Optimization

Perform deep analysis on:

Critical paths

False/multicycle paths

Clock domain crossings (CDC timing perspective)

Drive timing ECOs with minimal impact on power/area

Strong expertise in:

STA fundamentals (setup/hold, skew, jitter, latency)

OCV/AOCV/POCV concepts

SI effects and derates

Hands-on experience with:

Synopsys PrimeTime / Cadence Tempus

Deep understanding of:

Clock tree design and analysis

Low power (UPF/CPF) impact on timing

Advanced nodes (7nm, 5nm preferred)

Experience in hierarchical STA flows

Exposure to automation (TCL/Python scripting)

Knowledge of EM/IR and physical effects on timing

Experience working with global teams / customers

Zero/near-zero timing violations at tapeout

Clean signoff across all modes/corners

Predictable timing closure cycles

Strong correlation between block and top-level timing

Skill Requirements

Other Requirements

Apply now

Information at a Glance

Why HCLTech?

At HCLTech, youll supercharge your potential. Youll find your career. And youll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.