Senior System C Engineer

We are seeking an experienced SystemC Engineer to join our ASIC development team. The ideal candidate will have a strong background in SystemC modeling, digital signal processing (DSP), and ASIC development flows. This role involves developing high-level SystemC models, translating DSP algorithms into efficient SystemC implementations, and working closely with architecture, System, RTL, verification, and algorithm teams to enable system-level modeling and verification.

Responsibilities

• Develop and maintain high-performance SystemC models for complex optical systems and ASIC designs.
• Translate DSP algorithms from MATLAB into accurate and efficient SystemC implementations.
• Translate optical systems modeling into SystemC models
• Collaborate with architecture, RTL, and verification teams throughout the ASIC development lifecycle.
• Develop executable reference models for architecture exploration and functional validation.
• Support verification environments by integrating SystemC models into mixed-language simulation environments.
• Analyze and optimize model performance while ensuring functional accuracy.
• Debug and resolve functional issues across system-level.
• Participate in architecture definition, design reviews, and technical discussions.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Minimum 5 years of experience in SystemC development.
• Strong proficiency in SystemC, C++, and Transaction-Level Modeling (TLM).
• Experience with ASIC design and verification environments.
• Experience translating DSP algorithms from MATLAB to SystemC.
• Knowledge of digital signal processing concepts and fixed-point arithmetic.
• Hands-on experience with communication interfaces, including:
• Ethernet
• DSP-based communication systems
• Optical links/high-speed serial interfaces
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication skills and ability to work in cross-functional engineering teams.

Preferred Qualifications

• Experience with UVM and SystemVerilog verification environments.
• Familiarity with RTL design (Verilog/SystemVerilog/VHDL).
• Experience with high-speed networking or communication ASICs.
• Knowledge of scripting languages such as Python or Perl.
• Experience with performance modeling and architectural exploration.
• Familiarity with version control systems (Git) and continuous integration workflows.

Desired Skills

• Strong system-level thinking and architectural understanding.
• Ability to work independently while collaborating across multidisciplinary teams.
• Attention to detail with a focus on model accuracy and maintainability.
• Passion for solving complex technical challenges in ASIC and communication system development.