Senior Silicon Reliability Engineer, Amazon Leo

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Come work at Amazon!

The Role:

As Senior Silicon Reliability Engineer, you will engage with an experienced cross-disciplinary staff to conceive, design, and manufacture innovative semiconductor solutions for Kuiper's satellite and ground terminal products. You will work closely with internal inter-disciplinary teams and third-party suppliers to drive key aspects of semiconductor product manufacturing, test, qualification, and reliability to meet our customers' needs. You must be responsive, flexible and able to succeed within an open collaborative peer environment.

In this role you will:

• Review system and product specs and define appropriate qualification plans with PE, TE, & systems team.
• Review process & technology selection for product, based on application, design architecture and identify key reliability risks based on wafer level reliability qualification reports from foundry partners.
• Collaborate with packaging team in reviewing package design, configuration and BoM choices. Incorporate product-package considerations into char & qual plans.
• Develop & execute de-risking rel strategies to address technology risks for product qualification.
• Develop qualification strategies for multi-chip modules, optimizing for qual timelines and rel coverage.
• Design and fabricate burn-in boards for SoC and MCM product qualification.
• Review mission profile, application use conditions to develop qualification plans.
• Collaborate with design and DFT to generate test vector and activation profiles for burn-in.
• Bring-up & de-bug burn-in board at rel lab vendors and validate activation sequences.
• Identify and collaborate with rel lab vendors to execute qualification of SoCs and MCMs.
• Work with TE & PE teams to develop ATE test programs for qualification stresses.
• Estimate FIT rates and MTBF for ASIC components for system-level rel analysis.
• Run drift analysis from burn-in results and propose ATE limit guard banding.
• Identify root cause and drive fixes for any failures reported during qual.
• Publish detailed qualification report documenting completion of qual for upstream and downstream partners.

Export Control Requirement:

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities

• Own qual plan development and qualification for custom ASICs.
• Design, and debug qual hardware.
• Determine conditions, activation cycles and settings for qual execution.
• Debug failures from qual stresses.
• Publish final qual report upon completion of qual.
• Engage with packaging team to define packaging-related qualification considerations.
• Make system-level rel assessment from mission profile and qual results to system team.

A day in the life

Interface with system and design team to understand product requirements, features and mission profile. Engage with rel lab vendors to design qual HW and implement qual stresses. Work with test, packaging and product engineers in qual test program development and in reviewing results of ATE read-outs from different qual stresses.

About the team

The silicon rel engineering role is within the product engineering group of the silicon development org, and includes team members with a wide variety of experience, background and skillsets across the semiconductor industry, across advanced digital, RF and analog companies. Across the broader silicon org, the team includes experienced digital & RFIC designers, CAD teams and packaging engineers who interact with the product engineering team on a daily basis.