Senior Modem ATE Test Engineer , Amazon Leo

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Come work at Amazon!

The Role

As a Senior Modem ATE Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions for custom silicon powering the Leo network. You will lead the development of high-volume production test methodology for complex SoCs and modem devices, working closely with internal inter-disciplinary teams and third-party suppliers to drive key aspects of test definition, execution, and optimization.

You will own digital ATE test development end-to-end on Advantest 93K and/or Teradyne UltraFLEX platforms, from bring-up and pattern conversion through characterization, correlation, and production release. You will develop and debug structural and functional test content including scan/ATPG, MBIST and memory repair, and other DFT-based tests, as well as high-speed SERDES/HSIO test for complex modem and/or ASIC/SoC devices. You must be responsive, flexible, and able to succeed within an open, collaborative peer environment, and you will influence ASIC design, DFT, and manufacturing teams to ensure our products are architected for testability and cost-effective high-volume manufacturing.

Export Control Requirement

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities

In this role you will:

• Develop, debug, and release digital test programs for complex ASIC/SoC and modem devices on Advantest 93K and/or Teradyne UltraFLEX platforms.
• Build and debug scan/ATPG test content (stuck-at, transition, and other fault models) for complex ASIC/SoC and modem devices.
• Implement MBIST and memory repair flows.
• Characterize silicon performance and process variation through ring oscillator and process monitor tests.
• Test and debug I/O interface such as I3C, SPI, and GPIO.
• Optimize high-speed SERDES/HSIO test, including equalization, jitter/eye characterization, BER, and loopback.
• Convert test patterns from the DFT team into tester-suitable formats (e.g., STIL/WGL to native tester formats) and validate them on hardware.
• Bring up and characterize new devices, define test conditions (timing and levels), and drive shmoo/characterization to establish robust production limits and guard bands.
• Lead device correlation between wafer sort and final test, resolving systematic offsets and measurement issues.
• Reduce test time and cost across digital and DC test content while maintaining test coverage and quality.
• Design and review final test (FT) and wafer sort (WT) hardware, including load board, socket, and probe card designs, for best layout practices and signal/power integrity, particularly for high-speed digital interfaces.
• Partner with ASIC design and DFT teams to ensure devices meet Amazon standards for design-for-test and design-for-manufacturability in advanced process nodes.
• Analyze production data using statistical methods (Cp/Cpk, yield analysis) to drive continuous improvement in yield, quality, and test efficiency.
• Actively identify test-related readiness gaps, issues, and optimization opportunities throughout the product lifecycle and drive them to resolution.
• Support qualification activities such as burn-in board design, HTOL, and ESD.
• Mentor and provide technical guidance to junior test engineers, lead technical reviews, and set best practices for the test development team.