Senior FPGA Design Engineer

Pay Range: $85.00hr - $90.00hr

Job Overview:

The Senior FPGA Engineer will be part of the key design team, responsible for the delivery of FPGAs for defense applications. The candidate will architect and implement FPGA designs, with hands-on design and debugging primarily using Ethernet, I2C, SPI, and AXI protocols. The organization utilizes state-of-the-art EDA flows and methodologies including Mentor EDA (Simulator Questa Prime, Verification IP, UVM framework, Clock Domain Crossing, Reset Domain Crossing, Questa Lint), Client (DC/Primetime/Synplify), and Xilinx/Client/Microchip EDA (Vivado/Libero/Quartus). This is a high-impact role within the organization to ensure robust quality and delivery of communication products for National Security.

Work Environment:

The work environment is mainly computer and office based.

Responsibilities:

• Derive FPGA design specifications from system requirements.
• Develop detailed FPGA architecture for implementation.
• Implement design in RTL (VHDL) and perform module level simulations.
• Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA).
• Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Static Formal EDA.
• Generate verification test plans and perform End to End Simulations.
• Support Board and FPGA bring up.
• Validate design through HW/SW integration test with test equipment.
• Support product collateral for NSA certification.

Qualifications:

• Bachelor of Science (BS), Masters (MS), or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science).
• 5-7+ years of experience designing FPGA products with VHDL.
• Experience with Xilinx FPGAs and Vivado.
• Experience with Revision control systems.
• Experience with Earned Value Management (EVM).
• Strong verbal, written, and presentation skills.
• Active DoD Security Clearance.

Preferred Additional Skills:

• Experience with mapping algorithms to architecture.
• Experience in C++ (OOP).
• Experience with protocols such as Ethernet, TCP/IP, PCIe, NVMe, or USB.
• Experience with Xilinx SoC design with SDKs and PetaLinux OS.
• Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult.

Due to nature of job The candidate must have Ability to sit or stand for extended periods of time.