Senior Digital Design Engineer

The Opportunity
 

Our client is a globally recognized leader in memory interface and digital control technologies, with a strong presence in data center, cloud computing, and communications markets. This is a foundational growth hire for their U.S. headquarters.
 

The site is currently approximately 60 engineers with a strategic roadmap to scale to 250+ over the next 5–10 years. This offers the stability of a global leader with the "early-in" influence of a scaling site, allowing you to help shape the technical culture and mentorship of the growing team.
 

Summary
 

They’re seeking a Senior to Staff-level Digital Design Engineer (typically 4–12+ years of experience) to architect and develop RTL for a range of products. This role focuses on digital control systems (PMICs) as well as clock buffers and synchronizers. The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to provide technical leadership within a growing organization.
 

Key Responsibilities
 

Contribute as an individual designer and technical mentor within a collaborative environment.

Design and implement logic and state machines using SystemVerilog/Verilog RTL.

Develop, debug, and validate RTL using industry-standard simulation, synthesis, and analysis tools (including LEC, CDC/RDC, lint, DFT, and STA).

Generate PPA (power, performance, area) estimates, schedules, and detailed RTL design specifications.

Collaborate with verification and AMS teams to ensure functionality, performance, and coverage goals are met.

Support top-level integration, including floorplanning and digital/analog co-design.

Work closely with cross-functional stakeholders to identify requirements and drive continuous improvements.

Qualifications and Skills

Experience: 4–12+ years of relevant industry experience in digital design (Leveling available from Senior to Staff).

Design Depth: Strong background in high-speed, low-power design using advanced deep submicron technologies.

RTL: Proficiency in SystemVerilog/Verilog for both simulation and synthesis.

Tools: Experience with industry tools such as Design Compiler and PrimeTime.

Scripting: Experience with Perl, Tcl, and/or Python.

Mindset: Strong communication skills with a proactive, ownership-driven mindset and a willingness to mentor junior talent.

Preferred Qualifications

Experience with embedded microcontrollers (e.g., RISC-V).

Knowledge of digital control circuits for PMIC applications.

Familiarity with clock buffers and synchronizers.