Senior Design Verification Engineer

Pyramid, Inc

San Jose, CA

Apply

JOB DETAILS

SALARY

$150,000–$160,000 Per Year

JOB TYPE

Full-time

SKILLS

ASIC Design, Analog/Digital Converter, Analysis Skills, Artificial Intelligence (AI), Automation, Cadence, Communication Skills, Computer Engineering, Consulting, Cross-Functional, Debugging Skills, Design Verification, Digital/Analog Converter, Electrical Engineering, Employee Benefits, Git, Industry Standards, Information Technology & Information Systems, Intrusion Prevention Systems, Mentor Graphics, Mixed Signal Circuits, PLL/DLL, Perl Programming Language, Problem Solving Skills, Protocol Design, Python Programming/Scripting Language, RTL Design, Scalable System Development, Schematics, Scripting (Scripting Languages), Short Messaging Service (SMS), Simulation, Source Code/Configuration Management (SCM), Synopsys Tools, System-on-a-Chip (SoC), SystemVerilog, Systems Analysis, Tcl-Tk, Technical/Engineering Design, Verification Engineering, Verification Plans

LOCATION

San Jose, CA

POSTED

9 days ago

Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job ID:26-19462 Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Design and develop reusable UVM-based verification environments, including UVM agents, scoreboards, checkers, monitors, and behavioral models. Create and execute randomized and directed test cases to achieve functional and code coverage goals. Develop and maintain SystemVerilog Assertions (SVA) for protocol and design verification. Verify complex digital and mixed-signal (MXS) IPs and SoCs at both block and system levels. Analyze and debug simulation failures at the RTL and gate-level, including working with gate-level netlists and SDF timing simulations. Collaborate with RTL designers to identify, isolate, and resolve design issues. Develop scalable and reusable verification architectures and methodologies. Utilize scripting languages such as Perl, Python, or Tcl for automation and regression management. Work with industry-standard EDA simulation tools from Synopsys, Cadence, and Siemens Mentor Graphics. Manage source code using Git or DesignSync. Participate in design reviews, verification planning, and coverage closure activities. Work effectively within global cross-functional engineering teams. Key Requirements and Technology Experience: Must have skills: ASIC/SoC Design Verification, SystemVerilog, UVM, and SystemVerilog Assertions (SVA) and Synopsys, Cadence, and Mentor Graphics. Experience: 6–10+ Years Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of experience, or Master's degree with 6+ years of experience. 6+ years of experience in ASIC/SoC Design Verification. Strong expertise in SystemVerilog, UVM, and SystemVerilog Assertions (SVA). Experience verifying designs at both block and system levels. Experience with RTL, gate-level verification, netlists, and SDF timing simulations. Experience verifying mixed-signal circuits, including: PLL DLL ADC DAC Strong debugging skills involving RTL, gate-level simulations, and analog/mixed-signal schematic analysis. Hands-on experience with Synopsys, Cadence, and Mentor Graphics simulation tools. Experience with scripting languages such as Python, Perl, or Tcl. Experience with version control systems such as Git or DesignSync. Excellent analytical, communication, and problem-solving skills. Ability to work independently and within distributed global teams. Our client is a leading IT Industry, and we are currently interviewing to fill this and other similar fulltime positions. If you are interested in this position, please apply online for immediate consideration. Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here. #Del

Senior Design Verification Engineer

Pyramid, Inc

San Jose, CA

About the Company

Pyramid, Inc

Similar Job Searches