Senior Design Verification Engineer - CPU Subsystem

Experience: 5-12+ Years

Responsibilities

• Verify CPU subsystem and standard interfaces using SystemVerilog/UVM.
• Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
• Verify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling.
• Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
• Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Experience verifying CPU subsystems or SoC integration.
• Good understanding of AXI/AHB/APB and standard SoC interfaces.
• Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
• Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).