Senior Design Automation Engineer

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

We are seeking a Senior Design Automation Engineer to join our hardware team and contribute to the physical design of advanced IC packages and PCBs for next-generation machine learning and data center ASICs.

In this role, you will develop automation to enable physical design teams to execute Package and PCB products from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities

• Develop and deploy efficient design methodologies to support Package and PCB layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Evaluate industry EDA offerings and make recommendations for purchase and usage of advanced packaging features to design 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
• Deliver custom design automation to improve RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
• Contribute to cross-level teams for co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
• Develop data integration flows for co-design data across Package, PCB and SI/PI flows.
• Develop software in the following languages: Python, Skill, TCL. Utilize AI coding agents to speed development and iteration.
• Identify preferred methodologies to integrate physical verification checks (DRC, connectivity, shorts/opens) into physical design cycles.
• Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout methodologies - impedance-controlled routing, power plane optimization, and critical net shielding.

About the team

Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we're building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.