We are seeking a Senior Analog Design Engineer to develop power management and clocking IP for Treo-based SoCs. This role is a hands-on contributor expected to take ownership of complex analog blocks while collaborating across design, verification, and validation teams.
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world's most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
Qualifications - Minimum
- 5+ years of experience in analog IC design.
- Experience designing power management and/or clocking circuits.
- Solid understanding of analog circuit design, device physics, and layout effects.
- Proficiency with SPICE/AMS simulation and mixed-signal verification.
- Ability to work independently and communicate technical issues effectively.
Qualifications - Preferred
- Experience with Verilog-A/AMS modeling.
- Exposure to automotive or industrial applications.
- Interest in AI-assisted design and automation workflows.
Key Responsibilities
- Design, simulate, and verify analog IP including LDOs, DC/DC converters, charge pumps, PLLs, DLLs, and oscillators.
- Own analog blocks from specification through silicon validation.
- Perform schematic design, layout review, post-layout verification, and corner analysis.
- Collaborate with digital, validation, and technology teams during integration and bring-up.
- Support lab characterization and post-silicon debugging.
- Document designs and develop reusable IP methodologies.
Tools, Flows & Quality
Use industry-standard schematic capture and SPICE/AMS simulation tools. Perform PVT, noise, jitter, reliability, and aging analysis as part of design sign-off.
Innovation & Automation
Apply scripting and automation techniques to improve design efficiency and quality.
Success Metrics
- On-time delivery of analog IP blocks.
- High-quality silicon results with robust PVT coverage.
- Strong cross-functional collaboration and technical execution.
Key Responsibilities
- Design, simulate, and verify analog IP including LDOs, DC/DC converters, charge pumps, PLLs, DLLs, and oscillators.
- Own analog blocks from specification through silicon validation.
- Perform schematic design, layout review, post-layout verification, and corner analysis.
- Collaborate with digital, validation, and technology teams during integration and bring-up.
- Support lab characterization and post-silicon debugging.
- Document designs and develop reusable IP methodologies.
Tools, Flows & Quality
Use industry-standard schematic capture and SPICE/AMS simulation tools. Perform PVT, noise, jitter, reliability, and aging analysis as part of design sign-off.
Innovation & Automation
Apply scripting and automation techniques to improve design efficiency and quality.
Success Metrics
- On-time delivery of analog IP blocks.
- High-quality silicon results with robust PVT coverage.
- Strong cross-functional collaboration and technical execution.