RTL Design Engineer, Machine Learning Accelerators

Google LLC

Sunnyvale, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), Algorithms, Artificial Intelligence (AI), Best Practices, Blog, Cloud Computing, Code Reviews, Computer Architecture, Computer Engineering, Computer Science, Cookies, Customer Service Management, Customer Support/Service, Debugging Skills, Design Verification, Electrical Engineering, English Language, Equal Employment Opportunity (EEO), General Handyperson, Genetics, Government, Graphic Design, Greek Language, International Business, International Sales, Investor Relations, Low Power, Machine Learning, Mechanical Engineering, Memory Hardware, Network Operations Center, Operations Research, Perl Programming Language, Product Engineering, Product Management, Product Support, Public Affairs, Public Policy, Python Programming/Scripting Language, RCS (Revision Control System), RTL Design, Recruiting/Staffing Agency, Refactoring, Regulatory Requirements, Reliability Engineering, Risk, Sales, Sales Management, Scripting (Scripting Languages), Software Engineering, Solution Sales, SystemVerilog, Technical/Engineering Design, Testing, Verilog Hardware Description Language
LOCATION
Sunnyvale, CA
POSTED
30+ days ago

RTL Design Engineer Machine Learning Accelerators - Google Careers

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RTL Design Engineer Machine Learning Accelerators

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Experience driving progress solving problems and mentoring more junior team members deeper expertise and applied knowledge within relevant area.

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Minimum qualifications Bachelors degree in electrical engineering computer engineering computer science or a related field or equivalent practical experience. 4 years of experience with custom silicon design e.g. SoCs ASICs etc.. Experience with RTL design using Verilog or SystemVerilog.

Preferred qualifications Masters degree or PhD in electrical engineering computer engineering or computer science with a focus on computer architecture. Experience interacting with software architecture and other cross-functional teams. Experience with a scripting language e.g. Python or Perl Experience applying engineering best practices e.g. code review testing refactoring. Knowledge of processor design accelerators or memory hierarchies and machine learning algorithms. Knowledge of high performance and low power design techniques.

About the job In this role youll work to shape the future of AIML hardware acceleration. You will have an opportunity to drive cutting-edge TPU Tensor Processing Unit technology that powers Googles most demanding AIML applications. Youll be part of a team that pushes boundaries developing custom silicon solutions that power the future of Googles TPU. Youll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AIML-driven systems.

The AI and Infrastructure team is redefining whats possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale efficiency reliability and velocity. Our customers include Googlers Google Cloud customers and billions of Google users worldwide. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more.

The US base salary range for this full-time position is 138000-198000 bonus equity benefits. Our salary ranges are determined by role level and location. Within the range individual pay is determined by work location and additional factors including job-related skills experience and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only and do not include bonus equity or benefits. Learn more about benefits at Google.

Responsibilities Understand the overall application of the chip proposing and developing improvements in overall design. Design and document one or more blocks of an ASIC including functionality and timing. Work with software teams on functionality interfaces and documentation.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve creating a culture of belonging and providing an equal employment opportunity regardless of race creed color religion gender sexual orientation gender identity expression national origin disability age genetic information veteran status marital status pregnancy or related condition including breastfeeding expecting or parents-to-be criminal histories consistent with legal requirements or any other basis protected by law. See also Googles EEO Policy Know your rights workplace discrimination is illegal Belonging at Google and How we hire.

If you have a need that requires accommodation please let us know by completing our Accommodations for Applicants form.

Google is a global company and in order to facilitate efficient collaboration and communication globally English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies Google does not accept agency resumes. Please do not forward resumes to our jobs alias Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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