Principal, Design Verification Engineer, UAL and PCIe Subsystems

Principal, Design Verification Engineer, UAL and PCIe Subsystems
Santa Clara, CA – Onsite
Full Time

The Principal Design Verification Engineer will develop and architect functional verification environments for next-generation multi-core SoCs. This role involves creating sophisticated verification methodologies, writing comprehensive verification plans, developing constrained-random verification environments, debugging complex hardware issues, and collaborating closely with design engineers to ensure robust silicon validation.

What You Can Expect
In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.

Activities may include:
• Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
• Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.
• Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
• Unit and regression testing of software tools.

What We're Looking For
•BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering, 10-12 years of relevant professional experience.
• Experience with System Verilog, UVM.
• Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
• Experience with scripting language such as Python or Perl and EDA Verification tools.
• Experience with Object-Oriented Design and implementation.
• Good understanding of Linux O.S.
• Good programming skills desired, especially C++ and ARM assembly.
• Prior working knowledge of UAL or PCIe protocols

Other Skills:
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
• Requires the ability to accept and work with differing opinions.
• Cannot be a close-minded developer.
• Must be able to learn on the fly and work in a fast-paced environment.

Recruiter Submission Template –

Full Name:
Degree (BS/MS/PhD) – Major, University & Completion Year:
Total ASIC/SoC Design Verification Experience (Years):
Experience with SystemVerilog (Years – details):
Experience with UVM (Years – details):
Experience writing Verification Test Plans (Yes/No – details):
Experience building Constrained Random Verification Environments (Yes/No – details):
Experience with Coverage-Driven Verification (Yes/No – details):
Experience with Python and/or Perl Scripting (Years – details):
Experience using EDA Verification Tools (Specify tools):
Experience with Object-Oriented Programming (Yes/No – details):
Linux Experience (Years – details):
C++ Programming Experience (Years – details):
ARM Assembly Experience (Yes/No – details):
Experience with UAL Protocol (Yes/No – details):
Experience with PCIe Protocol (Years – details):
Experience verifying Multi-Core SoCs (Yes/No – details):
Experience with Boot Code Verification (Yes/No – details):
Motivation / Reason for interest in this position:
Contact Number:
Email ID:
LinkedIn Profile URL:
Full Address (Street, City, State, Zip Code):
Notice Period:
Current Work Authorization Status:
Expected Salary:
Are you able to relocate on your own expenses and work Santa Clara, CA – Onsite?