Physical Design Manager

Role- Physical Design Manager Location- San Jose, CA (Onsite) Job Type- Fulltime Role Overview We are seeking a highly experienced Physical Design Engineer to lead end-to-end implementation and optimization of advanced SoC designs. The ideal candidate will have strong expertise in physical implementation, timing convergence, low-power design, and advanced semiconductor process technologies, along with the ability to drive methodology improvements and collaborate across engineering teams.

Role- Physical Design ManagerLocation- San Jose, CA (Onsite)Role Overview

We are seeking a highly experienced Physical Design Engineer to lead end-to-end implementation and optimization of advanced SoC designs. The ideal candidate will have strong expertise in physical implementation, timing convergence, low-power design, and advanced semiconductor process technologies, along with the ability to drive methodology improvements and collaborate across engineering teams.

Key Responsibilities

• Own the physical implementation lifecycle from netlist to GDSII, including synthesis, floorplan development, placement, clock-tree implementation, routing, and final timing/signoff closure.
• Drive physical design optimization for advanced-node technologies (5nm and below), with a strong focus on performance, power, and area.
• Implement and debug low-power architectures using UPF, including power-domain integration and related SoC-level challenges.
• Analyze and resolve complex issues involving timing constraints, SDC, hierarchical integration, and UPF propagation across IP/SoC boundaries.
• Develop and enhance automation and productivity solutions using Tcl, Python, Perl, and/or Shell scripting.
• Work closely with RTL, STA, power, DFT, IP, methodology, and other cross-functional teams to achieve design milestones and tape-out readiness.
• Support physical signoff activities, including timing, power integrity, physical verification, and design quality checks.
• Identify opportunities to improve implementation methodologies, flows, and overall design efficiency.
• Provide technical leadership and mentorship to junior engineers and contribute to team development.

Required Qualifications

• 10+ years of industry experience in semiconductor physical design, implementation, and timing closure.
• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline, or equivalent industry experience.
• Proven experience with RTL-to-GDSII implementation and successful tape-outs using 5nm or more advanced process technologies.
• Strong understanding of SoC physical design, including floorplanning, placement optimization, clock and power network implementation, routing, and timing convergence.
• Hands-on experience with industry-standard EDA tools such as Synopsys Design Compiler/ICC2/PrimeTime, Cadence Genus/Innovus, Ansys RedHawk/Voltus, and Calibre or equivalent tools.
• Solid understanding of advanced process-node effects and their impact on physical implementation, timing, power, and layout quality.
• Practical knowledge of low-power implementation and UPF-based power intent management.
• Strong scripting and automation capabilities using Tcl, Python, Perl, or Shell.
• Demonstrated ability to lead technical discussions and effectively collaborate with cross-functional engineering teams, IP teams, and external EDA partners.
• Strong problem-solving, communication, ownership, and mentoring skills.