Physical Design Engineer - STA Design Integration

Insight Global is looking for 2 Junior to Mid level STA Design Integration Engineers for a world class semiconductor ASIC provider. As a STA DI Engineer you will join a highly skilled team of engineers that own the timing analysis and sign-off of complex ASICs. You will be responsible for the day-to-day timing closure and sign-off of complex ASIC designs, run and analyze static timing analysis (using tools like Synopsys PrimeTime or Cadence Tempus), debug timing violations such as setup/hold failures, and refine or create timing constraints to accurately model real chip behavior. You will investigate issues related to clock distribution (including PLLs and clock trees), signal integrity, and RC effects, while interpreting detailed timing reports and tool warnings to identify root causes. The role also involves writing scripts (Python, TCL, Bash) to automate flows, process large datasets, and improve efficiency, as well as leveraging knowledge of circuit elements like flip-flops, latches, memory, and CMOS logic to understand timing paths.

This is a direct hire position sitting out of the Fort Collins, CO location, and offering between $107k - $200k based on experience. The role also offers bull benefits package, annual bonuses, substantial RSU packages, and full relocation provided.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to HR@insightglobal.com.To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy:

Required Skills & Experience
- Bachelors in Electrical or Computer Engineering with 5+ years of experience, or Masters Degree with 4+ years
- 4+ years of experience in ASIC Physical Design with an emphasis on STA and timing
- Experience writing scripts in Python, TCL, and/or Bash
- Basic understanding of PLLs and clock networks
- Familiar with design elements like flip flops, latches, memories, and logic gates
- Experience with STA tools like Synopsys PrimeTime, Cadence Tempus, Siemens Tessent
- Understanding of RC networks and how they affect the timing/propagation of signals
- Understanding of signal integrity, crosstalk delay, and glitch/noise analysis
- Understanding of setup analysis, hold analysis, and other timing checks
- Experience using SPICE analysis

Nice to Have Skills & Experience

+ Experience with advanced STA concepts;
- POCV/SOCV/LVF modeling of variation
- MIS - multi input switching
- CCS/ECSM/NLDM - liberty timing models
- PBA - path based analysis
- LOCV/SOCV - location aware timing derates

Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.