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Job Description:

About Altera

At Altera, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from netlist through physical implementation and sign-off. You will be responsible for executing physical design tasks at the block and subsystem level, helping optimize designs for performance, power, and area (PPA) while meeting quality and schedule requirements.

You will collaborate with design, architecture, DFT, CAD/EDA, and other engineering teams to resolve implementation challenges and support successful design delivery. This is an opportunity to develop your expertise in physical design and gain exposure to the unique implementation requirements of advanced FPGA technologies.

Key Responsibilities

• Execute physical design implementation activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECOs, extraction, and physical design sign-off for assigned blocks or subsystems.

• Analyze and optimize designs for timing, power, and area (PPA) to meet project requirements.

• Perform static timing analysis and timing closure, identify critical paths, and work with design teams to resolve timing issues.

• Review and debug physical implementation issues related to placement, congestion, clocking, routing, timing, and design constraints.

• Support physical verification activities including DRC, LVS, and related sign-off checks and help resolve identified issues.

• Work with RTL, architecture, DFT, CAD/EDA, and other engineering teams to understand design requirements and resolve physical implementation challenges.

• Apply established physical design methodologies and flows using industry-standard EDA tools.

• Develop basic scripts or automation, using Tcl, Python, Perl, Shell, or similar languages, to improve productivity and automate repetitive physical design tasks.

• Support block-level integration activities, including physical constraints, pin placement, timing constraints, and interface requirements.

• Participate in design reviews, documentation, and continuous improvement of physical design processes and methodologies.

• Contribute to successful tape-out by completing assigned implementation tasks and resolving physical design issues within established project schedules.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. 

$118,900 - $169,895 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

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Qualifications:

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 4+ years of industry experience in physical design, physical implementation, or SoC/ASIC backend design, including:

• 4+ years of hands-on experience with digital ASIC and/or SoC physical design, including exposure to floorplanning, placement, clock tree synthesis (CTS), routing, ECO implementation, and physical sign-off.

• Experience using industry-standard EDA physical design and sign-off tools such as Synopsys IC Compiler II, Fusion Compiler, PrimeTime, Cadence Innovus, or equivalent tools.

• Experience with static timing analysis and timing closure, including analyzing timing reports and helping resolve setup and hold violations.

• Experience working with physical design constraints, including clocks, timing constraints, placement constraints, and design rules.

• Experience debugging common physical implementation issues such as timing violations, congestion, routing issues, and design rule violations.

• Familiarity with physical verification activities including DRC, LVS, and related physical sign-off checks.

• Ability to work effectively with RTL design, architecture, DFT, CAD/EDA, and other engineering teams throughout the physical implementation process.

• Basic scripting or automation experience using Tcl, Python, Perl, Shell, or similar programming languages is preferred.

• Understanding of semiconductor physical design concepts including power planning, placement, clocking, routing, timing closure, and physical verification.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

• Experience with advanced semiconductor process technologies such as 16nm, 10nm, 7nm, 5nm, or below.

• Experience with FPGA or programmable logic device physical implementation.

• Familiarity with FPGA architectures, including programmable logic, routing fabrics, configurable logic blocks, I/O structures, and on-chip interconnect.

• Experience with full-chip or hierarchical physical implementation flows.

• Experience with low-power physical design concepts such as clock gating, power domains, power intent, or power-aware implementation.

• Experience with physical design automation or scripting using Tcl, Python, Perl, or Shell.

• Familiarity with power integrity concepts such as IR drop, electromigration (EM), and signal integrity.

• Exposure to physical design sign-off methodologies and manufacturing considerations.

• Experience working in a collaborative, cross-functional semiconductor engineering environment.

• Exposure to AI/ML-assisted physical design optimization tools or methodologies is a plus.

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