Physical Design Engineer 7452

Taiwan Semiconductor Manufacturing Co Ltd

CA

JOB DETAILS
SALARY
$110,000–$160,000 Per Year
SKILLS
Academic Background, Analysis Skills, Business Model, CAD/CAM (Computer-Aided Design/Computer-Aided Manufacturing), Cadence, Circuit Design, Communication Skills, Computer Science, Cross-Functional, Csh (C Shell) Scripting, Customer Support/Service, DFT (Design for Test), DRC Flows, Design Flows, Design Verification, Detail Oriented, Digital Circuits, Diversity, Ecosystems, Electrical Engineering, Electricity, Electronics, Equal Employment Opportunity (EEO), Floorplanning, Genetics, Government, Import/Export, Integrated Circuits (ICs), International Operations, Leading Edge Technology, Licensing, Low Power, Manufacturing, Performance Management, Performance Tuning/Optimization, Presentation/Verbal Skills, Problem Solving Skills, Python Programming/Scripting Language, Quality Monitoring, RC Extraction, Regulations, Reporting Dashboards, Research & Development (R&D), Sales, Schematics, Scripting (Scripting Languages), Semiconductor Manufacturing, Semiconductors, Signal Integrity, Static Analysis, Static Timing Tools, Synopsys Tools, System Integration (SI), System-on-a-Chip (SoC), Tcl-Tk, Team Player, Technical Leadership, Technical/Engineering Design, Testing, Timing Verification, Unix Shell Programming, VLSI, Verilog Hardware Description Language, Writing Skills
LOCATION
CA
POSTED
30+ days ago

Company: TSMC Technology Inc. Location: USA - California Employment Type: Regular Posted: Mar 23 2026

Overview of Role Are you a highly motivated and skilled Physical Design Engineer with at least 3 years of industrial experience eager to push the boundaries of semiconductor technology? Join our dynamic Test Chip Physical Implementation team in San Jose, CA and play a critical role in bringing TSMCs most advanced process nodes (A16, A14, A10) to life. This is an exciting opportunity for an engineer with a strong foundation in VLSI design, a passion for innovation, and hands-on experience with cutting-edge EDA tools. You will be instrumental in the physical implementation and tapeout of complex test vehicles, contributing directly to the future of high-performance computing and advanced electronics.

Responsibilities

  • Drive the end-to-end physical implementation and tapeout of test vehicles on TSMCs leading-edge process nodes (A16, A14, A10).
  • Execute comprehensive physical design flows from netlist-to-GDS, including:
  • Block and SoC-level floorplanning
  • Power grid implementation
  • Low-power structure integration
  • Advanced placement, clock tree synthesis (CTS), and routing for optimal performance and congestion management.
  • Extensive design optimization for power, performance, and area (PPA) targets.
  • Perform rigorous design signoff verification encompassing:
  • RC extraction
  • Static Timing Analysis (STA)
  • IREM analysis
  • Design Rule Check (DRC)
  • Layout Versus Schematic (LVS)
  • Electrical Rule Check (ERC)
  • Voltage-Aware Layout Parasitic (VCLP) analysis
  • Achieve robust timing closure, physical design closure, and power/signal integrity closure based on comprehensive signoff verification results.
  • Actively contribute to the development and evaluation of advanced methodologies and flows to meet aggressive PPA goals.
  • Develop and enhance CAD automation scripts and dashboards using TCL, Python, CSH, and other scripting languages to streamline design flows and ensure quality monitoring.
  • Collaborate effectively with cross-functional teams including RTL, DFT, and CAD to provide insightful feedback and ensure seamless integration throughout the design cycle.

Minimum Qualifications

  • Masters Degree or higher in Electrical Engineering or Computer Science with a strong academic background in VLSI-related coursework and projects.
  • A minimum of 3 years of industrial experience in physical design or a closely related field within the semiconductor industry.
  • Demonstrated expertise in digital circuit concepts and a deep understanding of the full physical design implementation flow (auto placement and route, STA, layout design, physical verification, IREM signoff).
  • Hands-on experience with major EDA tools from Synopsys (e.g., ICC2, DC, Primetime, StarRC, ICV) and Cadence (e.g., Innovus, Virtuoso, SimVision).
  • Proficiency in scripting languages such as Python, TCL, CSH, Verilog, and Unix shell scripting.
  • Strong analytical and problem-solving skills with meticulous attention to detail.
  • Excellent written and verbal communication skills with the ability to articulate complex technical concepts clearly.
  • Positive, collaborative, self-motivated, and adaptable team player capable of thriving in a fast-paced, diverse cultural environment.

Preferred Qualifications

  • Prior internship or professional experience in physical design, circuit design, or related semiconductor roles.
  • Experience in optimizing placement strategies, congestion removal, and post-placement timing closure.
  • Familiarity with clock tree synthesis techniques to mitigate latency and skew.
  • Knowledge of Power Integrity (PI) and Signal Integrity (SI) closure techniques.
  • Experience with multi-voltage design concepts and low-power techniques.
  • Familiarity with other EDA tools such as Ansys Redhawk or Synopsys Fusion Compiler.
  • DFT knowledge is a plus.

Company Description As a trusted technology and capacity provider, TSMC is driven by the desire to be the worlds leading dedicated semiconductor foundry-the technology leader with a strong reputation for manufacturing excellence. Advancing semiconductor manufacturing innovations to enable the future of technology.

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the worlds leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industrys leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be required by the U.S. Government.

Diversity Statement TSMC Technology Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer, valuing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at g_accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMCs obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.

Pay Transparency & Benefits Statement At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $110,000 and $160,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individuals skills, qualifications, education, experience, and the position level and location.

TSMCs total compensation package consists of market-competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.

About the Company

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Taiwan Semiconductor Manufacturing Co Ltd