Physical Design Engineer - 175558

Responsibilities: of the Physical Design Engineer: Execute full RTL-to-GDSII physical design flow including synthesis, floor planning, place and route, CTS, and timing closure. Perform static timing analysis, ECO implementation, and MMMC timing signoff activities. Conduct physical verification including DRC, LVS, antenna checks, and design signoff. Analyze and resolve signal integrity, IR drop, electromigration, and power integrity challenges. Collaborate with RTL, verification, DFT, and system teams to optimize design quality, performance, and power. Qualifications: of the Physical Design Engineer: 5+ years of experience in ASIC/SoC physical design and implementation for advanced semiconductor products. Hands-on expertise with Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus, and Calibre verification tools. Strong understanding of RTL-to-GDSII flow, STA, physical verification, low-power methodologies, and timing closure. Experience with advanced process nodes including FinFET technologies and hierarchical or full-chip integration. Proficiency with Tcl, Perl, Python, Linux/Unix environments, and design flow automation. Compensation: for the Physical Design Engineer includes: Salary range depends on experience Comprehensive benefits package including medical, dental, vision, 401(k), and paid time off. This job opens for applications on 10/02/2026. Applications for this job will be accepted for at least 30 days from the posting date.