PHY RTL Design Engineer

Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

Develop signal processing intensive design for wireless communication SoCs, including:

• Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model.
• Architecting area and power.
• Efficient low latency designs with scalabilities and flexibilities.
• Work with algorithm and software team to ensure performance and power efficiency.
• Power and Area efficient RTL logic design, and DV support.
• Running tools to ensure lint and CDC/RDC clean design.
• Synthesis and timing constraints.
• Experience in design of signal processing Wireless protocols.
• RTL coding and verification for PHY modem development.
• Support banckend activities by reviewing the reports and appropriate adjustment of the design.
• Involve in the pre and post silicon bringup process.

Qualifications:

• Bachelors degree in related field.
• Understanding of DSP fundamentals.
• Digital Communications knowledge.
• Proficiency in RTL Design.
• Familiarity with UVM DV environment and AI based efficiency improvement flows.
• Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
• Understanding of Decoders - Viterbi, LDPC, Polar.
• Understanding of Filter design, multi-radix implementation, and compromises.
• Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
• Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
• Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
• Background in computer architecture.
• Bus fabric, especially APB/AHB/AXI.
• Power management with multiple power domains.
• Ability to work well in a team and be productive under ambitious schedules.
• Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
• Experience with FPGA and/or emulation platform desired.
• Excellent communication skills - both written, and oral.