PCIe Silicon Validation & Debug Engineer

Pyramid, Inc

Sunnyvale, CA

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JOB DETAILS

SALARY

$43–$47 Per Hour

JOB TYPE

Full-time

SKILLS

Analysis Skills, Artificial Intelligence (AI), Computer Engineering, Computer Firmware, Computer Skills, Consulting, Data Quality, Debugging Skills, Debugging Tools, Electrical Engineering, Employee Benefits, Equalization, Error Handling, FPGA, Failure Analysis, IP (Internet Protocol), Information Technology & Information Systems, Injections, Intellectual Property Development, Interoperability Testing, Logic Analyzer, Maintain Compliance, Oscilloscope, PCI, PCI Express (PCI-E), PHY, Perl Programming Language, Power Management, Protocol Analysis, Prototyping, Python Programming/Scripting Language, Quality Metrics, Root Cause Analysis, Scripting (Scripting Languages), Short Messaging Service (SMS), Signal Integrity, Silicon Bringup, System Validation, System-on-a-Chip (SoC), SystemVerilog, Tcl-Tk, Test Automation, Test Design, Test Plan/Schedule, Test Suite, Testing, Validation Plan, Validation Testing

LOCATION

Sunnyvale, CA

POSTED

6 days ago

Immediate need for a talented PCIe Silicon Validation & Debug Engineer. This is a 06+ months contract opportunity with long-term potential and is located in Sunnyvale CA (Remote; for all over US). Please review the job description below and contact me ASAP if you are interested. Job ID: 26-22150 Pay Range: $43 - $47/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Pre-Silicon Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling Collaborate with design teams on coverage closure, assertions, and functional coverage models Post-Silicon Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon) Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance Debug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues Drive compliance and interoperability testing per PCI-SIG specifications Analyze PCIe specification updates and assess impact on existing IP/SOC designs Automate test infrastructure, result parsing, and regression frameworks Document findings, debug methodologies, and test coverage metrics Contribute to team knowledge sharing Key Requirements and Technology Experience: Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field Experience: 3–8+ years of experience in PCIe validation, verification, or silicon bring-up Strong understanding of PCIe specification (Gen3 through Gen5/Gen6), including: Transaction Layer: TLP types, ordering rules, flow control, completion handling Data Link Layer: ACK/NAK, replay, LCRC, DLLP Physical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b) Power management: ASPM, L-states, D-states Proficiency in System Verilog/UVM for pre-silicon test development Experience with protocol analyzers and lab debug tools for post-silicon validation Familiarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing Solid understanding of PCIe enumeration, BAR programming, and configuration space Experience with FPGA prototyping or emulation platforms is a plus Experience with CXL (Compute Express Link) or other PCIe-based protocols Knowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis) Familiarity with compliance testing per PCI-SIG specifications and test suites Experience with NVMe, CCIX, or UCIe protocols Background in SoC-level integration and system-level validation Understanding of BIOS/firmware interactions with PCIe subsystems Contributions to PCIe IP development or architecture definition ("PCIe Engineer" OR "PCI Express Engineer" OR "Silicon Validation Engineer" OR "Validation Engineer" OR "Post Silicon Validation Engineer" OR "Pre Silicon Validation Engineer" OR "Silicon Debug Engineer") AND (PCIe OR "PCI Express") AND (Validation OR Verification OR Debug OR "Silicon Bring-up") AND (SystemVerilog OR UVM OR Python) Our client is a leading IT Industry and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration. Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here. #Del

PCIe Silicon Validation & Debug Engineer

Pyramid, Inc

Sunnyvale, CA

About the Company

Pyramid, Inc

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