Lead SoC Performance & Power Engineer

About the role

As our Lead Performancearchitect, you'll drive the architectural configuration, system-level simulation, and PPA optimization of the chiplet by using industry-standard ESL toolsand / ordeveloping in-housetoolsto integrate and calibratehighspeed I/O IPs such asPCIe, UCIeand Ethernet as well asNoCfabricinto a system.You'llownthe trade-off analysis thatdefinewhat we tape out.

Responsibilities

• Own PPA exploration andtrade-offsbetween peak performance, silicon area, and thermal/power budgets, and turn that into clear tape-out recommendations.

• Build transaction-level models (TLM)usingcommercial ESL suites (e.g.Platform Architect) that integrate third-partyIPs such asPCIe, UCIe, and NoCetcinto a full-chiplet model.

• Define, sweep, andvalidatehardware configuration parameters — buffer sizes, queue depths, clock-domain crossings, routing tables — to maximize throughput and minimize latency across realistic workloads.

• Characterize traffic across the internal NoC and the UCIe die-to-die interface to find congestion points and rule out protocol deadlocks before they reach silicon.

• Work directly with our IP vendors to debug model/behavioral mismatches, report performance anomalies, and integrate new IP deliverables as they land.

Required

• BS/MS in Electrical Engineering or related fieldwith6+ years in computer architecture, performance modeling, or microarchitecture configuration.

• Direct, hands-on experience with commercial ESL tools such as Platform Architect,Virtualizer, or comparable frameworks.

• Solid working knowledge of at least one of: PCIe (Gen 5/6/7), UCIe, or AMBA NoC protocols (AXI/CHI) — and a willingness to get deep on the others.

• Strong Python for automating large-scale simulation sweeps, parsing performance reports, and analyzing results.

• Familiarity withSystemCand transaction-level modeling paradigms — enough to write custom traffic generators when the off-the-shelf models fall short.

Nice to have

• Fluency with powermodeling or floor-planning trade-offs.

• Prior workon a multi-die / chiplet program, or hands-on UCIe die-to-die.

• Experience taking architectural modelsthrough toa real tape-out.

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.