Lead ASIC Digital Design Engineer

Basic Qualifications: Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience. Company Overview: General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation.

Basic Qualifications :

Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.

 

LEARANCE REQUIREMENTS:
Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibilityrequirements for access to classified information. Due to the nature of work performed within our facilities, U.S.citizenship is required.

 

 

Responsibilities for this Position:

We're looking for a skilled Lead ASIC Digital Design Engineer who has meaningful hands-on experience in RTL design and has contributed to complex digital hardware development. This is a technical role for someone who understands the full ASIC/FPGA design lifecycle and is ready to take on real ownership within a collaborative, high-performing team.

 

If your career has been primarily running P&R tools, this probably isn't the right fit. We need an RTL designer at heart — someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions.

 

The right candidate is a self-starter who operates with minimal supervision — someone who takes ownership of their work, drives progress independently, and brings solutions rather than waiting to be directed.

 

 

What You'll Do

 

  - Own RTL design — Develop and lead RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification

  - Drive timing closure — Work through synthesis, place and route, and static timing analysis; understand root causes of timing failures and own fixes through resolution

  - Lead verification efforts — Develop and execute test and simulation plans; verify results and drive closure on failures

  - Own JIRA triage — Review and prioritize incoming issues; maintain an accurate and actionable backlog

  - Lead code reviews — Conduct RTL code reviews, setting technical standards and providing actionable feedback

  - Support program planning — Provide input to Integrated Master Schedule (IMS) development and Earned Value (EV) reporting; communicate accurate task status and schedule risk

  - Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing accurate technical input on scope, complexity, and level of effort for ASIC/FPGA design tasks

  - Evaluate technology — Assess foundry technologies, device libraries, IP cores, and EDA tooling to inform design decisions

  - Collaborate broadly — Participate in Integrated Product Teams and working groups across divisions or companies

 

 

What We're Looking For

 

 

  - 8–12+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer

  - Experience contributing to ASIC tape-out efforts, including timing closure and physical verification

  - Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a meaningful differentiator

  - Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)

  - Working knowledge of:

    - RTL design and microarchitecture

    - Bus fabric design and verification

    - Clock domain crossing (CDC) analysis

    - Reset sequencing and validation

    - Timing closure at advanced nodes

    - Power analysis and optimization

 

 Skills & Knowledge

 

  - Strong understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows

  - Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)

  - Ability to operate independently — identifying problems, driving resolution, and keeping work moving without requiring day-to-day direction

  - Ability to evaluate vendor and foundry capabilities

  - Proficiency in JIRA for issue tracking and backlog management

  - Proficiency in Microsoft Office for documentation and communication

 

 

Why This Role

 

You won't be handed a spec and told to code. You'll take real ownership across the design lifecycle, with technical latitude to shape how problems get solved. This is a role where your work matters, your growth is supported, and the team values engineers who take initiative and see problems through to resolution.

 

Salary Note: This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range: USD $176,512.00 - USD $187,000.00 /Yr. Company Overview:

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans