Lead ASIC DFT Staff Engineer

Role: Lead ASIC DFT Staff Engineer
Location Remote (must be aligned with PST time zone)

Let's create our future together at The AES Group!

About The AES Group
The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that have the greatest positive impact on society. AES has helped over 40 business enterprises, including Fortune 500 companies, engage their customers, empower their employees, and transform their business operations with the power of cloud, data, AI, engineering, and other emerging technologies.

Position Overview:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

• Lead DFT architecture, implementation, verification & sign-off
• Drive scan architecture, scan insertion, scan stitching & compression
• Own ATPG, MBIST/LBIST, DRC, coverage & diagnosis
• Work with JTAG, Boundary Scan, iJTAG & SSN
• Develop and validate DFT SDC and timing constraints
• Lead silicon bring-up, post-silicon debug & root-cause analysis
• Collaborate with RTL, Verification, Physical Design, STA & Silicon teams
• Develop DFT automation using Tcl, Perl or Python
• Mentor DFT engineers and drive best practices

Required Skills

• 8+ years of hands-on ASIC DFT experience
• Strong expertise in Scan, ATPG, MBIST/LBIST & DFT debug
• Experience with Synopsys, Cadence and/or Siemens/Mentor EDA tools
• Hands-on experience with scan insertion, ATPG, DRC & coverage analysis
• Experience with MBIST implementation/verification; SMS preferred
• Strong post-silicon debug and silicon bring-up experience
• Experience with large, complex ASIC/SoC designs and hierarchical DFT flows
• Strong understanding of RTL, synthesis, LEC and physical design
• Scripting experience with Tcl, Perl or Python