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Hardware Design and Failure Analysis Engineer(Networking Exp)

Saransh Inc

  • San Jose, CA
  • 7 days ago

    Highlights

    Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies. Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.

    Numbers & Facts

    LocationSan Jose, CA

    Description

    Job Title: Hardware Design and Failure Analysis Engineer (Networking)
    Location: Onsite San Jose, CA.

    Job Description :

    • High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
    • Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.
    • Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
    • Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
    • Strong background in Networking, Routers, and Switches is highly preferred.
    • Hands-on design experience with PCIe Gen4/Gen5/Gen6 and DDR4/DDR5 is essential.
    • Candidates should have experience designing complex hardware platforms rather than only troubleshooting failures.

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