GPU DFT Design Verification Engineer

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, GPU. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. As a DFT Verification engineer your primary responsibilities will include:

• Reviewing Architecture and Design Specifications
• Extracting design features and developing attributes and verification plans
• Working with designers to verify DFT implementation and run various checks
• Implementing test benches, generating advised/constrained random tests
• Debugging failures, running gate level simulations, supervising bugs, and closing coverage
• Handling schedules and supporting multi-functional engineering effort
• Assisting in verification flows, automation scripts and regressionsBachelors Degree + 3 Years of ExperienceProven experience in large processors and/or GPU/SOC designs Hands-on experience in directed or random verification, coverage analysis and assertions Proficient in scripting languages such as Perl, Python or TCL Strong Object-Oriented Programming skills Solid Understanding of Design Verification (DV) methodologies for verifying DFT implementation in pre-silicon Excellent skills in problem solving, communication and desire to seek new challenges Experience working under strict schedule deadlines with the ability to manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus