Design Verification Engineer

47Billion

San Jose, CA

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JOB DETAILS

SALARY

$170,000 Per Year

JOB TYPE

Full-time

SKILLS

RTL Design, FPGA Design, Technical/Engineering Design, FPGA, VHDL Hardware Description Language, Verilog Hardware Description Language, Timing Verification, SystemVerilog, Design Verification, ASIC (Application Specific Integrated Circuit), RTL Verification, ModelSim, PCI Express (PCI-E), ASIC Design, System-on-a-Chip (SoC), Tcl-Tk, Hardware Design, IP (Internet Protocol), Simulation, Integrated Circuits (ICs), Test Bench, ASIC Verification, Static Timing Tools, Integrated Circuit (IC) Design, Circuit Design, Verification Engineering, Verification Plans,

QUALIFICATIONS

Required Skills:

· Strong hands-on with SystemVerilog and UVM

· Experience in block-level verification

· Good understanding of digital design fundamentals

· Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

Exposure to low-power verification (UPF)

Experience with AMBA protocols (AXI/AHB/APB)

RESPONSIBILITIES

· Develop and maintain UVM-based verification environments

· Create test plans, testcases, and coverage models

· Perform functional verification of RTL designs

· Debug RTL and testbench issues

· Drive coverage closure (functional + code)

BENEFITS

Paid Time-Off, Paid Sick Days, Medical, Dental, Vision

LOCATION

San Jose, CA

POSTED

10 days ago

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Design Verification Engineer

47Billion

San Jose, CA

About the Company

47Billion

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