FPGA Engineer III job opportunity at Tucson, AZ

  • $93–$97.86 Per Hour

Highlights

Look for candidates with experience in one or more of the following: FPGA / Signal Processing. Indotronix is seeking an FPGA Engineer III for an exciting job opportunity in Tucson, AZ.

Numbers & Facts

LocationTucson, AZ
Salary$93–$97.86 Per Hour

Description

  • Current Openings
  • Veterans Program
  • Working With Indotronix
  • Referral Program

All current openings

FPGA Engineer III job opportunity at Tucson, AZ

  • Location: Tucson, Arizona 85756
  • Work model: On-site
  • Posted 2 weeks ago
  • Job ID: JPC - 210605

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Job Description

Indotronix is seeking an FPGA Engineer III for an exciting job opportunity in Tucson, AZ.

Job Title: FPGA Engineer III

Location: Tucson, AZ 85756

Duration: 12 Months Contract

Pay Rate: $93/hr to $97.86/hr on W2

Note: Active clearance to Start

Job Description

  • FPGA architecture and system design
  • Translating system requirements into FPGA requirements
  • VHDL design and coding
  • FPGA verification and validation
  • Functional and code coverage analysis
  • Integration and hardware debugging
  • Production FPGA releases
  • Technical documentation creation
  • Supporting design reviews and program milestones

Must-Have Qualifications

Candidate MUST have:

  • Minimum 8+ years of FPGA engineering experience
  • Strong digital design and VHDL coding experience
  • Experience with Xilinx and/or Microsemi FPGA devices and tool flows
  • Experience delivering FPGA solutions for system-level applications
  • Hands-on integration and debug experience
  • U.S. Person status required based on defense-related work

Preferred Qualifications

Look for candidates with experience in one or more of the following:

FPGA / Signal Processing

  • Radar processing
  • Image processing for visual or infrared sensors
  • Digital Signal Processing (DSP)

Embedded Systems

  • ARM processors
  • MicroBlaze
  • Nios processors

Communications

  • Gigabit serial interfaces
  • Multi-Gigabit Transceivers (MGTs)

Verification

  • SystemVerilog
  • UVM (Universal Verification Methodology)
  • Constrained random verification
  • Veloce emulation platform

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Job details

Job ID JPC - 210605

Location Tucson, Arizona, United States

Work Model On-site

Experience 8-15 years

Pay Rate $93 - $97.86

Posted September 29, 2026

Skills FPGA VHDL

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