Founding Silicon Engineer

Bronco

  • San Francisco, California
  • 30+ days ago

    Highlights

    Contribute to the architecture of Bronco's domain-specific reasoning systems — defining task structure, expected agent behavior, and quality criteria across DV workflows. Deploy and integrate Bronco into customer workflows, working directly alongside verification teams at leading chip companies.

    Numbers & Facts

    LocationSan Francisco, California

    Description

    About the Role

    As a Founding Silicon Engineer, you will be the domain backbone of Bronco's AI agents. You'll contribute to the architecture of our reasoning systems, drive tool integrations with industry-standard EDA environments, and shape product direction based on what you know from the inside — the workflows, pain points, and failure modes that only come from real verification experience.

    This role puts you at the intersection of AI and silicon at a unique moment. You'll have a front row seat into a diverse range of chip projects across the industry — from AI accelerators to SoCs to custom silicon — and you'll be fundamentally changing how chips are made. The ideal candidate is an experienced silicon or verification engineer who has spent real time inside industry CAD flows. We have a strong preference for founding engineers, early-stage engineers, and past founders.

    What You'll Do

    • Contribute to the architecture of Bronco's domain-specific reasoning systems — defining task structure, expected agent behavior, and quality criteria across DV workflows
    • Own and expand tool integrations between Bronco's AI and EDA environments — simulators, coverage tools, linters, and formal verification platforms
    • Work hands-on with CAD and EDA tooling to build, test, and validate AI-generated outputs against real verification environments
    • Deploy and integrate Bronco into customer workflows, working directly alongside verification teams at leading chip companies
    • Feed onsite learnings back into product direction and tool integration roadmap

    We'd Like to See

    • You are an exceptional engineer who can solve any problem
    • 2+ years of experience in ASIC/SoC design and verification
    • Hands-on familiarity with industry-standard EDA tooling — Synopsys, Cadence, Questa, or equivalent
    • Strong expertise in digital verification, SystemVerilog, and UVM
    • Proficiency in scripting languages and programming (Python, Tcl, Perl, or equivalent)
    • Excellent debugging skills across simulation, waveform analysis, and coverage closure
    • Strong communication and collaboration abilities

    We'd Prefer If You Had

    • Experience deploying or integrating EDA tools into automated flows or CI pipelines
    • Exposure to formal verification methods
    • Interest in AI and machine learning applications in chip design
    • Experience working at a startup or in a high-ownership engineering environment

    What We Offer

    • Competitive salary and equity package
    • Comprehensive benefits including health, vision, dental, and 401(k)
    • Housing stipend
    • High-ownership, high-velocity environment with rapid learning opportunities
    • A technical problem that is the present rate limiter on the future

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