On-die: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address-translation (NTB/ATT) setup, MSI-X and AER handling, reset/FLR, power management, telemetry, and in-field firmware update. Stand up the firmware engineering infrastructure: CI, automated and HIL testing, requirements traceability, secure-development practices (secure boot, attestation, key management), and the RAS/error-handling and fault-attribution strategy.
Own the end-to-end firmware/embedded-software architecture for TYLsemi chiplets.
Define the firmware/hardware interface together with the Chip Architectsfor a seamless HW-to-SW handoff; define the MCU subsystem (MCU SS) architecture from the firmware point of view; and define the chip's debug interface and debug features.
On-die: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address-translation (NTB/ATT) setup, MSI-X and AER handling, reset/FLR, power management, telemetry, and in-field firmware update.
Host-side: kernel drivers, the device-virtualization/transparency shim (synthetic PCIe device, VFIO-mdev-class), management libraries/APIs, and IOMMU (VT-d/SMMU) coordination.
Define the hardware/software boundary with architecture and RTL — datapath (credit, ordering, merge/split, address-translation execution) in RTL; control plane in firmware — and own register maps and UCIe sideband/mailbox protocols.
Define a unified flow for firmware development and DV test cases, with a single source of truthshared across firmware and DV (register models, stimulus, and sequences), and drive HW/SW co-verification.
Stay hands-on through first silicon.
Bring-up, Methodology & Quality
Drive pre-silicon firmware and host-software development on emulation, and virtual platforms, and lead post-silicon bring-up and debug.
Stand up the firmware engineering infrastructure: CI, automated and HIL testing, requirements traceability, secure-development practices (secure boot, attestation, key management), and the RAS/error-handling and fault-attribution strategy.
Define firmware release, quality, and security criteria across products and customers.
Cross-functional & Customer Collaboration
Be the technical bridge between firmware/software and architecture, RTL, DV, PHY/IP vendors and program management — bringing software feasibility into hardware decisions early.
Work directly with customers: compute-SoC partners on PCIe/CXL enablement, ATE/SLT integrators on the firmware and management libraries.
Technical Leadership & Ownership
Set technical direction, roadmap, and clear subsystem ownership (boot/security, PCIe/CXL management, host drivers and virtualization, RAS/telemetry).
What We're Looking For
BS/MS in Electrical / Computer Engineering or Computer Science
12+ years of embedded firmware development, with at least 5 years in silicon-level bring-up and validation of high-speed interface IPs.
Working knowledge of design verification (DV) and HW/SW co-simulation / co-verification flows, and the ability to define a unified firmware + DV test flow with a single source of truth.
Expert-level C and assembly for resource-constrained embedded CPUs (RISC-V or Arm Cortex-M/R class); strong debugging skills using JTAG/OpenOCD, trace, and logic analysers.
Deep PCIe expertise: link-training state machine, equalization, speed-change sequences, LTSSM register-level behaviour.