Engineering (US) - Consulting Engineer 3

Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams and play a key role in full chip design integration with the testability features coordinated in the RTL.

We are currently seeking a "DFT (Design for Test) Lead" for a Contract role with one of our clients. Please apply if you are interested and available for it.

Title: DFT (Design for Test) Lead
Duration: 12+ Months Contract
Location: 100% Remote

Responsibilities:

• Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

 
Qualifications:

• Bachelor’s or a master’s degree in electrical or computer engineering required.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high-speed digital/analog macros.
• Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, Tempus/Primetime.
• At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production.

Regards,
Ishika Sharma
Cell: 973.967.3386
Email: ishika.sharma@artech.com