Engineer: Verification - III

You will be responsible for driving RTL design and verification activities across all phases of development, ensuring robust functionality across operating modes, corner cases, power states, and SoC integration. " Knowledge of low-power design methodologies, including UPF, multi-power-domain architectures, power intent verification, clocking strategies, reset architectures, and synchronization techniques.

Prefers onsite 4 days per week. (Open to remote only candidates)
MRUNDA required
RTL Design and Verification
Position Overview
PROM-based solutions are critical for mobile, IoT, client, networking, and server products.
We are seeking an experienced RTL Design and Verification Engineer to develop and verify PROM Fuse Soft IP solutions, including controllers, subsystems, and reusable IP components.
In this role, you will collaborate closely with design, verification, architecture, and integration teams to deliver high-quality, production-ready solutions. You will be responsible for driving RTL design and verification activities across all phases of development, ensuring robust functionality across operating modes, corner cases, power states, and SoC integration.
Successful candidates will possess strong technical expertise, demonstrate ownership of deliverables, and excel in solving complex design and verification challenges.
The ideal candidate combines deep knowledge of digital design and verification methodologies with strong scripting and automation skills. Expertise in SystemVerilog coding and either Formal Verification or UVM-based verification is essential.
Strong written and verbal communication skills are required. Candidates must be able to create clear and concise design, verification, and validation documentation, effectively communicate technical issues and recommendations, and provide responsive support to internal and external SoC customers throughout IP integration and deployment.
Minimum Qualifications
" Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience.
" Proven experience designing and verifying complex RTL designs, IPs, subsystems, or SoCs.
" Strong understanding of digital design fundamentals, RTL microarchitecture, and verification methodologies.
" Ability to interpret specifications and datasheets, translate requirements into robust architectures and RTL implementations, and identify risks, corner cases, and verification requirements.
" Proficiency in SystemVerilog and industry-standard design, simulation, lint, CDC, RDC, and verification tools.
" Strong expertise in one or more of the following areas:
" Formal Verification:
- Property checking and assertion-based verification.
- Model checking and equivalence checking.
- Proof convergence and formal signoff methodologies.
- Hands-on experience with Cadence JasperGold.
" UVM-Based Functional Verification:
- Verification architecture and UVM testbench development.
- Constrained-random and coverage-driven verification.
- Assertions, scoreboards, checkers, and debug methodologies.
- Verification planning, execution, and closure.
" Strong analytical, debugging, and problem-solving skills.
" Ability to independently drive design and/or verification activities from planning through signoff, including coverage closure, issue resolution, and quality improvements.
Preferred Qualifications
" Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of industry experience.
" Experience defining RTL microarchitectures and developing corresponding verification strategies.
" Experience with both Formal Verification and UVM-Based Functional Verification, coverage analysis, metrics-driven closure, and regression management.
" Knowledge of low-power design methodologies, including UPF, multi-power-domain architectures, power intent verification, clocking strategies, reset architectures, and synchronization techniques.
" Strong understanding of finite state machine design, datapath implementation, and verification best practices.
" Familiarity with common SoC interfaces and protocols such as APB, AHB, AXI, JTAG, scan, and fuse-programming interfaces.
" Experience with scripting and automation using languages such as Python, Perl, Tcl, or Shell.
" Experience supporting IP integration, debugging customer issues, and collaborating with cross-functional teams to drive successful product execution.
What Sets Skilled Candidates Apart
" Strong sense of ownership and accountability.
" Ability to independently drive complex technical initiatives and deliver results.
" Excellent collaboration and communication skills across geographically distributed teams.
" Passion for quality, automation, and continuous improvement.
" Customer-focused mindset with a commitment to timely execution and support.

EEO

Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.