Edge & Physical AI HW Product Manager/Director

NXP Semiconductors NV

  • San Jose, CA
  • 10 days ago

    Highlights

    Lead make-vs-buy-vs-IP-license assessments for new capabilities including MAC array architectures like in-memory compute, non-uniform memory subsystems, memory architectures and interconnect IP like UCIe. Own the competitive benchmarking framework - track competing NPU silicon from Qualcomm, Nvidia, RockChip, Hailo, Axelera, Ambarella, and others; define differentiation strategy on formfactors, performance, power, cost, safety, support and software ecosystem.

    Numbers & Facts

    LocationSan Jose, CA

    Description

    Job Responsibilities:

    • Define and maintain the multi-generational hardware roadmap across discrete NPUs (Ara series), i.MX-integrated NPU IP, and chiplet-based scale-out architectures
    • Translate customer requirements and competitive intelligence into silicon product specifications including performance targets (TOPS, TOPS/W, TOPS/sq.mm), memory architecture, power, I/O, packaging, safety and process node decisions
    • Drive product definition through architecture review, design partitioning, and feature tradeoff decisions in close collaboration with silicon architects and engineering leads
    • Own the business case for each hardware product - BOM cost, ASP, gross margin targets, volume projections, and NPV - and present investment recommendations to executive leadership
    • Lead make-vs-buy-vs-IP-license assessments for new capabilities including MAC array architectures like in-memory compute, non-uniform memory subsystems, memory architectures and interconnect IP like UCIe
    • Define chiplet strategy for scale-out NPU configurations - including die partitioning, die-to-die interface selection, and multi-chip package requirements to support larger model inference workloads
    • Partner with the i.MX, S32 SoC, i.MCU, and RT product teams to define NPU IP integration requirements, including power domains, bus interfaces, memory bandwidth allocation, software-hardware co-design constraints, SoC bring-up, and debugging.
    • Drive early access and customer sampling programs; gather validated product requirements from lead customers and feed them into architecture decisions before freeze
    • Own the competitive benchmarking framework - track competing NPU silicon from Qualcomm, Nvidia, RockChip, Hailo, Axelera, Ambarella, and others; define differentiation strategy on formfactors, performance, power, cost, safety, support and software ecosystem
    • Manage product lifecycle from definition through ramp, sustaining, and EOL - including customer transition plans across generations
    • Represent the NPU hardware portfolio to NXP executive leadership, customers, partners, and at industry events
    • Co-own SW development of dNPU, integrated and chiplet based designs w/ the SW product manager
    • Develop end-to-end system solutions and demonstration platforms for hardware and software developers at industry events and conferences.

    Job Qualifications:

    • 10+ years of product management or product strategy experience in semiconductor or silicon IP, with direct ownership of hardware product definition and roadmap
    • Hands-on experience defining silicon product specifications - performance targets, memory architecture, power envelopes, packaging, and process node decisions
    • Strong understanding of SoC and IP integration - experience defining IP for integration into a host processor or SoC is strongly preferred
    • Familiarity with chiplet architectures and multi-chip interconnect standards (UCIe, BoW, or equivalent) is a significant plus
    • Track record of driving design wins and customer adoption across multiple product generations
    • Ability to build and defend business cases including BOM cost, ASP, gross margin, and market sizing
    • Experience with competitive analysis and differentiation strategy in a fast-moving semiconductor segment
    • Strong cross-functional leadership skills - ability to drive alignment across architecture, engineering, sales, marketing, and executive stakeholders
    • Excellent written and verbal communication skills; able to represent complex technical tradeoffs to both engineering teams and executive audiences

    Good to have:

    • Direct experience in AI/ML inference silicon - NPU, GPU, or inference accelerator product management
    • Familiarity with inference workloads including CNNs, transformers, LLMs, and VLM variants deployed at the edge
    • Experience working with ODMs, OEMs, and contract manufacturers on board design, system integration, and production
    • Background in industrial, automotive, or embedded edge markets
    • MBA or advanced degree in Electrical Engineering, Computer Engineering, or related discipline

    More information about NXP in the United States...

    NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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