Design Verification Engineer, Staff

Role Overview

Astera Labs is seeking a Staff Design Verification Engineer with a talent for breaking code and developing creative verification approaches for complex AI connectivity ASICs. Using your expertise in SystemVerilog, UVM, and problem-solving skills, youll contribute to the functional verification of cutting-edge designs supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

Youll be responsible for the full verification lifecycle-from planning to test development to debugging and coverage closure-while collaborating with RTL designers and system validation teams. This is an exciting opportunity to grow your career at a hypergrowth company defining the future of AI infrastructure connectivity.

Key Responsibilities

• Verification Execution

• Execute full verification lifecycle using SystemVerilog/UVM methodologies, from test planning through coverage closure

• Develop test sequences and constrained-random stimulus to exercise design functionality and corner cases

• Identify and implement coverage measures to ensure comprehensive verification and high-quality tape-out

• Debug & Collaboration

• Debug failures collaboratively with RTL designers, driving issues to root cause resolution

• Deploy hybrid verification techniques combining directed and constrained-random approaches

• Work with software and system validation teams to develop and execute test plans on emulation platforms

• Infrastructure & Process

• Contribute to verification infrastructure improvements and automation using scripting tools

• Support regression infrastructure and coverage analysis workflows

• Document test plans, coverage strategies, and verification results

Basic Qualifications

• Bachelors degree in Electrical Engineering; Masters preferred
• 5+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
• Strong proficiency with SystemVerilog/UVM-based verification methodologies
• Experience developing test plans, test sequences, and coverage closure strategies
• Knowledge of industry-standard simulators, revision control systems, and regression systems
• Ability to work independently and collaboratively with cross-functional teams

Preferred Qualifications

• Masters degree in Electrical Engineering or related field
• Experience with Verification IPs for protocols such as PCIe, CXL, Ethernet, DDR4/5, or similar
• Exposure to formal verification methods
• Working experience with scripting tools (Python/Perl) to automate verification infrastructure
• Experience with directed test methodologies or cache verification

Compensation

• Base salary range is $160,000 to $195,000 depending on experience, level, and business need
• This role may be eligible for discretionary bonus, incentives, and benefits.