Design Verification Engineer

Redolent

  • Menlo Park, California
  • 30+ days ago

    Highlights

    Role- Design Verification Engineer Location- Menlo Park, CA Minimum Qualifications BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience. Hello, One of our direct client is urgently looking for Design Verification Engineer @ Menlo Park, CA.

    Numbers & Facts

    LocationMenlo Park, California

    Description

    Hello,One of our direct client is urgently looking for Design Verification Engineer @ Menlo Park, CA.Role- Design Verification EngineerLocation- Menlo Park, CAMinimum Qualifications
    • BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience
    • 3+ years of UVM experience (so this implies 3+ years of SystemVerilog as well)
    • Deep understanding of coverage, constrained-random, transaction level
    • Experience with Verdi/VCS is a must
    • Experience with test plan documentation
    • Familiarity with Python3/Bash/Tcl scripting is a must
    • Experience with debugging simulation failures to guide digital design
    • Experience with fixed-point arithmetic
    • Preferred Qualifications
    • BSEE/MSEE/BSCompE/MSCompE with 10 years of industry experience
    • Experience with performance analysis and performance characterization a plus.
    • Experience with using a Hierarchical Verification Plan is a plus.
    • Experienced with a full ASIC/SOC tape out from beginning to end
    • Experience with video processing or graphics pipelines is a plus
    • Experience with floating-point arithmetic in addition to fixed-point arithmetic

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