Job Description
MediaTek is seeking a Compute Subsystem Architect to define and build capability
in this space ahead of product commitment. The role covers the full Neoverse
Compute Subsystem scope: core configuration, CMN topology and parameterization,
cache/SLC architecture, and CHI coherency behavior. The role also provides
architectural guidance on chiplet and 3D-IC partitioning trade-offs, collaborating
with dedicated packaging and interconnect teams on interface definitions.
Responsibilities
- Architect compute subsystems (CPU cluster, L2/L3/SLC cache, coherent mesh
fabric) for next-generation ASIC and advanced Arm computing platform products.
- Own CMN topology recommendations: mesh dimension, HN-F/SN-F/RN-F placement,
SLC distribution, snoop filter policy, and QoS parameters.
- Build CPU subsystem performance models to quantify many-core scaling: latency,
bandwidth-per-core, and mesh congestion under AI-era workload traffic patterns.
- Drive technology readiness: track Arm Neoverse CSS/CMN roadmap, identify IP
gaps, and lead technical engagement with Arm on architecture and multi-die scope.
- Evaluate architectural implications of 3D-IC and chiplet splits on CMN topology,
CHI credit return, and snoop timing; hand off quantified constraints to
packaging and physical teams; co-design while maintaining focus on computing architecture.
- Align design with potential product landing vehicles including custom ASIC
solutions and advanced Arm platforms (including future CPU Dielet configurations).
- Prepare architecture specifications and technical documents; present trade-offs
to engineering leadership and executives.
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