| Location | CA |
Title: Senior Timing and Clocking Characterization Engineer
Location: Mountain View, CA
Work Model: Onsite / Hybrid
Let's create our future together at The AES Group!
About The AES Group
The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that have the greatest positive impact on society. AES has helped over 40 business enterprises, including Fortune 500 companies, engage their customers, empower their employees, and transform their business operations with the power of cloud, data, AI, engineering, and other emerging technologies.
Position Overview
We are looking for a Senior Timing and Clocking Characterization Engineer with strong expertise in custom clocking circuits, transistor-level characterization, Liberty timing models, and production static timing analysis (STA).
In this role, you will bridge analog circuit design and digital timing signoff by characterizing custom clocking blocks across process, voltage, and temperature (PVT) corners, developing signoff-quality timing models, and validating their behavior within block-level and full-chip timing environments.
The ideal candidate combines hands-on SPICE simulation and characterization expertise with practical experience in timing constraints, multi-mode multi-corner (MMMC) analysis, variation-aware timing, and design implementation handoff.
Key Responsibilities
Clocking Circuit Characterization: Characterize custom and mixed-signal clocking circuits, including delay-locked loops (DLLs), duty-cycle correctors (DCCs), digitally controlled delay lines, phase interpolators, and clock dividers across PVT corners.
Liberty Timing Model Development: Generate, validate, and maintain Liberty (.lib) models, including timing arcs, setup and hold checks, minimum pulse-width constraints, NLDM/CCS models, and LVF variation data, as applicable.
Timing and Circuit Analysis: Evaluate propagation delay, duty-cycle distortion, jitter contributions, lock range, delay resolution, and timing sensitivities. Correlate characterized models against SPICE simulation results.
Static Timing Analysis: Perform block-level and full-chip STA using Synopsys PrimeTime or Cadence Tempus. Debug timing violations and support timing closure across operating modes and corners.
SDC Constraint Development: Create and validate Synopsys Design Constraints (SDC), including generated clocks, false paths, multicycle paths, and other clock-related timing exceptions.
Characterization Flow Development: Develop and maintain automated characterization, data-processing, and STA workflows using Python, Tcl, Perl, or equivalent scripting tools.
Physical Design Integration: Support implementation and signoff handoff through extracted timing models (ETMs), parasitic extraction, and correlation with physical design tools such as StarRC or Quantus.
Cross-Functional Collaboration: Work closely with analog and custom circuit designers, digital design engineers, STA specialists, and physical design teams to resolve timing issues and improve signoff accuracy.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a closely related field.
7+ years of relevant experience in custom circuit timing, transistor-level characterization, timing model development, or static timing analysis.
Hands-on experience with SPICE-based characterization flows using Cadence Liberate/Liberate AMS, Synopsys PrimeLib/SiliconSmart, Synopsys NanoTime, or equivalent tools.
Production-level STA experience with Synopsys PrimeTime or Cadence Tempus, including MMMC analysis and OCV/AOCV/POCV methodologies.
Practical understanding of DLLs, duty-cycle correction circuits, delay lines, and custom clocking architectures.
Strong SPICE simulation experience using HSPICE, Cadence Spectre, Synopsys PrimeSim/FineSim, or equivalent simulators.
Proficiency in scripting with Python, Tcl, Perl, or similar languages for automation and flow development.
Ability to analyze complex timing behavior, correlate circuit-level simulation results with timing models, and debug signoff issues.
Preferred Qualifications
Experience with clocking architectures for DDR, LPDDR, HBM memory PHYs, SerDes, or die-to-die interfaces.
Experience with FinFET or gate-all-around (GAA) process technologies and participation in at least two silicon tapeouts.
Familiarity with physical design and implementation tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler.
Experience with extracted parasitic analysis and timing model correlation using StarRC, Quantus, or equivalent tools.
Exposure to characterization and validation across extended temperature ranges, including cryogenic operating conditions.
Terms & Conditions for Candidate Portal
Last Updated: May 6th, 2026
Please read these Terms & Conditions ("Agreement", "Terms") carefully before using the Candidate Portal ("Portal", "Service") provided by The AES Group ("we", "us", "our").
By accessing or registering for the Portal, you ("Candidate", "User", "you", "your") agree to be bound by these Terms.
If you do not agree with any part of these Terms, you may not use the Portal.
By accessing or using the Candidate Portal, you affirm that you are at least 18 years old and are legally authorized to enter into this Agreement.
If you are accessing the Portal on behalf of an employer or third party, you represent that you have the authority to bind that entity to these Terms.
The Portal is provided as a digital platform for Candidates to:
These Terms govern your use of the Portal and all related services.
You understand and agree that:
You agree to use the Portal in compliance with:
Prohibited actions include, but are not limited to:
You acknowledge that:
Your use of the Portal is subject to our Privacy Policy, which describes how we collect, use, and safeguard your personal information.
By using the Portal, you consent to the collection and use of information as described.
All intellectual property contained in or presented through the Portal is owned by us or our licensors.
You may not copy, modify, distribute, or otherwise use any Portal content without express written permission.
The Portal and all content and services are provided "as is" and "as available."
We make no warranties, express or implied, including:
To the fullest extent permitted by law, we are not liable for:
We may modify these Terms at any time.
Changes will be posted on the Portal with an updated "Last Updated" date.
Your continued use of the Portal after changes indicates your acceptance.
We may suspend or terminate your access to the Portal if you violate these Terms or for any reason, with or without notice.