Chip Package Signal and Power Integrity Engineer

Google LLC

Sunnyvale, CA

JOB DETAILS
SKILLS
3D Design, 3D Graphics Software, ASIC (Application Specific Integrated Circuit), Analysis Skills, Android, Artificial Intelligence (AI), Automation, Automation Engineering, Budgeting, C++ Programming Language, Cloud Computing, Cloud Storage, Computer Engineering, Computer Science, Consumer Packaged Goods, Cross-Functional, Customer Service Management, DVD (Digital Video Disk), Data Analysis, Data Processing, Design Verification, Develop Methodologies, Electrical Engineering, Electricity, English Language, Equal Employment Opportunity (EEO), Field Sales, Financial Services, Genetics, Graphic Design, HFSS (High Frequency Structure Simulator), IP (Internet Protocol), Japanese Language, Leadership, MATLAB, Manufacturing, Memory Hardware, Network Administration/Management, Network Operations Center, Operations Research, Power Engineering, Printed Circuit Board (PCB), Printed Circuit Board Design, Product Design, Product Management, Product Support, Python Programming/Scripting Language, Recruiting/Staffing Agency, Regulatory Requirements, Reliability Engineering, Retail, Sales, Sales Management, Signal Integrity, Simulation, Software Engineering, Static Analysis, Static Timing Tools, Stock Purchase Plans, System Architecture, System Integration (SI), System Validation, Technical Consulting, Timing Verification
LOCATION
Sunnyvale, CA
POSTED
19 days ago

Chip Package Signal and Power Integrity Engineer - Google Careers

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Chip Package Signal and Power Integrity Engineer

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Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

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Minimum qualifications:

  • Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

  • 10 years of experience with SI/PI design for chip/package or system PCB.

  • Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or SI/PI.
  • Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
  • Knowledge of next-generation memory and chiplet standards, including timing budget, design & sign-off methodologies.
  • Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
  • Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.
  • Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google"s most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s TPU. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Chip Package Signal integrity/Power Integrity (SI/PI) Engineer in the chip implementation team, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the package and system level. You will be part of a larger team with system architects, ASIC engineers, and other SI/PI engineers. You will work with cross-functional teams including chip design team, board design team, system design team and vendors. You will drive chip packaging signal and power implementations to meet chip, package and system electrical requirements.

Our computational challenges are so complex and unique we can"t purchase off-the-shelf hardware, we make it ourselves. We design and build the hardware, software and networking technologies that power all of Google"s services. You design and build the systems that are the heart of the world"s most powerful computing infrastructure. You will see systems from concept to high volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Drive chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for HPC based on 2.5D/3D package technology.
  • Develop Power integrity methodology for advanced package technology, and Methodology development to enhance accuracy and productivity.
  • Evaluate New package technology and development, and High speed Interface IP.
  • Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, define boundaries of chip design and explore SI/PI and DFM trad-eoff for package design closure for production.
  • Provide feedback on chip floorplan considering package/system routability and SI/PI.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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