| Location | Milpitas, CA |
Principal Layout Job Description
In this role, the layout engineer will work closely with the analog design team to layout and verify custom analog-mixed-signal IPs.
Lead full-custom IC layout design and verification, including:
• Chip floor planning • Analog IP layout • Chip level layout integration of various analog mixed-signal and ASIC blocks
Full verification of block level and top-level layout, including:
• Extraction • DRC (Design Rule Check) • LVS (Layout Versus Schematic) • DFM (Design for Manufacturability) checking
Layout schedule planning and working with other IP layout engineers to integrate various layout blocks.
Co-work with designers on block level and top-level floor planning.
Layout review for:
• Power • GND • Routing • Electro migration • Signal path check • Matching • Signal coupling