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ASIC/RTL Design Engineer

Saicon Consultants Inc

  • SAN JOSE, CA
  • 1 day ago

    Highlights

    JOB DUTIES: You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, Client/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Our modeling engineers are expected to contribute in all of the following areas: Reading schematics, netlists and circuit specifications to define what each model must capture.

    Numbers & Facts

    LocationSAN JOSE, CA

    Description

    JOB DUTIES:
    • You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, Client/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
    • Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers.
    • Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.
    Our modeling engineers are expected to contribute in all of the following areas:
    • Reading schematics, netlists and circuit specifications to define what each model must capture
    • Developing model architecture and accuracy targets, balancing fidelity against simulation speed
    • Writing behavioral SystemVerilog models of analog blocks
    • Validating models against transistor-level simulation results
    • Debugging simulation failures and finding the root cause in the model, RTL or testbench
    • Documenting model behavior, limitations and interfaces
    EXPERIENCE AND EDUCATION:
    • Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
    • Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
    • Familiarity with high-speed interface standards is a plus.

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