ASIC Physical Design Engineer

Responsibilities: of the ASIC Physical Design Engineer: Own physical design implementation activities from RTL-to-GDSII, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and timing closure. Perform static timing analysis (STA), signal integrity analysis, power integrity verification, and physical verification to achieve design signoff requirements. Collaborate closely with RTL, design verification, DFT, and architecture teams to resolve timing, power, and implementation challenges. Develop and enhance physical design methodologies, automation flows, and QoR optimization strategies using scripting and custom tools. Support advanced-node ASIC development for high-performance data center applications through tape-out and production readiness. Qualifications: of the ASIC Physical Design Engineer: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of ASIC physical design experience. Strong expertise in RTL-to-GDSII implementation flow, including Cadence Innovus, Synopsys ICC2, Fusion Compiler, Design Compiler, or Genus. Experience with STA tools such as PrimeTime or Tempus and hands-on timing closure, MMMC analysis, ECO implementation, and signoff. Knowledge of DRC/LVS verification, low-power methodologies (UPF/CPF), power integrity analysis, and advanced process nodes including FinFET technologies. Proficiency with Tcl, Perl, Python, Linux/Unix environments, and automation of physical design flows. Compensation: for the ASIC Physical Design Engineer includes: Competitive salary range depending on experience Comprehensive benefits package including medical, dental, vision, 401(k), PTO, and holiday This job opens for applications on 11/02/2026. Applications for this job will be accepted for at least 30 days from the posting date.