| Location | Beaverton, OR |
| Salary | $75,000–$110,000 Per Year |
Annual base salary 75000 - 110000 Responsibilities Member of design team for large SOCs Qualifications BSMS degree and 0-5 years of work experienceGood understanding of digital design and verification practices from course work or job experienceAbility to write Verilog RTL and basic knowledge or experience with simulationsFamiliarity with high-speed protocols such as USB3 or PCIe is a desirable Required Experience Demonstrate a basic knowledge of System Verilog SV or similar verification languageDemonstrate a basic knowledge of Verilog for chip design and verificationExperience with high-speed serial protocols USB3 PCIe Ethernet etc.Relevant course work for VLSIASIC design Taipei & Hsinchu Sr. Analog Design Engineer Sr. Logic Design Engineer Nanjing Sr. Analog Design Engineer Sr. Layout Designer Engineer Sr. Logic Design Engineer Sr. Software Engineer Sr. System Engineer Shanghai Sr. Analog Design Engineer Sr. FAE Engineer Sr. Layout Designer Engineer Sr. Logic Design Engineer Sr. Product Engineer Sr. Software Engineer Sr. System Validation Engineer Sr. System Engineer Sr. Test Engineer For any questions or further information contacthrparadetech.com