| Location | North Reading, MA |
Title: ASIC and Logic Design Engineering Manager
Location: North Reading, MA (Hybrid Schedule 3 days per week onsite)
Target Start Date: ASAP
Type: Direct Hire
PayRate / Salary (Ranges OK): $155,500 $248,700 annually + discretionary bonus
Position Overview
We are seeking an experienced ASIC and Logic Design Engineering Manager to lead a team of approximately 4 6 engineers responsible for designing, developing, integrating, and verifying complex FPGA solutions for next-generation technology products. This hands-on engineering leadership position requires extensive expertise in digital FPGA design, RTL development, simulation, verification, and hardware integration, along with a proven track record of leading complex engineering projects from concept through production release.
The ideal candidate will have experience developing complex FPGA System-on-Chip (SoC) designs for real-world products, managing multiple simultaneous development initiatives, and collaborating across FPGA design, mixed-signal ASIC design, circuit board design, software engineering, and systems engineering teams. This individual must be capable of providing technical leadership while remaining actively involved in RTL development, architecture decisions, and engineering problem-solving.
Key Responsibilities
" Lead, mentor, and provide technical direction to a team of approximately 4 6 FPGA design engineers, including oversight of remote engineering resources.
" Manage 2 3 simultaneous FPGA or digital IP development projects, ensuring successful execution from initial concept and architecture through design implementation, verification, lab validation, and production release.
" Develop and maintain engineering project schedules, budgets, resource plans, and technical milestones to ensure timely delivery of project objectives.
" Manage engineering staffing levels, including full-time employees and contract resources, while balancing workloads and project priorities.
" Establish performance goals, provide coaching, support professional development, and manage employee performance and compensation.
" Provide hands-on technical contributions to FPGA implementation, including RTL coding and complex digital logic design, as needed.
" Lead technical discussions involving FPGA architecture, design tradeoffs, implementation strategies, simulation, verification, and hardware integration.
" Collaborate with FPGA design and verification managers, mixed-signal ASIC designers, circuit board engineers, software developers, and systems engineers to define and implement new products.
" Oversee FPGA design verification, static timing analysis, digital simulation, and hardware validation activities to ensure functional and performance requirements are met.
" Provide technical support for hardware sustaining issues, debugging, root-cause analysis, and resolution of design or integration challenges.
" Represent the FPGA engineering team in project core team meetings, technical reviews, and program-level discussions.
" Identify technical risks, resource constraints, and potential schedule impacts while developing appropriate mitigation strategies.
" Drive FPGA engineering process improvements, design quality initiatives, and development best practices.
" Ensure FPGA and digital IP deliverables meet product specifications, technical requirements, quality standards, and project schedules.
Required Qualifications
" Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
" Minimum of 12 years of relevant experience in digital FPGA design and integration.
" Minimum of 5 years of experience as an FPGA/ASIC project lead, successfully driving multiple development projects from concept, architecture exploration, and design implementation through laboratory validation and production release.
" Extensive hands-on experience designing and integrating complex FPGA architectures and digital logic solutions for real-world hardware products.
" Extensive experience developing RTL code, preferably using Verilog.
" Extensive experience with digital simulation tools and methodologies.
" Extensive experience performing static timing analysis using industry-standard tools.
" Experience designing FPGA-based solutions incorporating PCI Express (PCIe), DDR3/DDR4/DDR5 memory interfaces, Advanced eXtensible Interface (AXI), Ethernet, Serial Peripheral Interface (SPI), and Serializer/Deserializer (SERDES) technologies.
" Experience developing FPGA designs using AMD/Xilinx or Client/Altera FPGA platforms and associated development tools, including Vivado or Quartus.
" Experience using digital design quality tools and methodologies, including LINT and Clock Domain Crossing (CDC) analysis.
" Familiarity with digital verification tools and methodologies.
" Experience using bug tracking and issue management systems such as Jira.
" Experience with source control systems such as ClearCase, Git, or CVS, along with continuous integration practices.
" Experience using project scheduling and planning tools such as Microsoft Project.
" Demonstrated ability to lead multiple complex FPGA or digital IP development projects while managing technical deliverables, schedules, budgets, and engineering resources.
" Strong understanding of FPGA design, implementation, verification, hardware integration, and debugging processes.
" Excellent written and verbal communication, presentation, technical leadership, and cross-functional collaboration skills.
Preferred Qualifications
" 2 3 years of experience as a first-level engineering manager responsible for leading, mentoring, and developing engineering teams.
" Experience with digital ASIC design and integration.
" Experience designing complex FPGA and digital ASIC System-on-Chip (SoC) architectures.
" Experience using Cadence digital simulation tools.
" Familiarity with Universal Verification Methodology (UVM) and advanced digital verification techniques.
" Experience with both AMD/Xilinx and Client/Altera FPGA architectures and development environments.
" Experience with embedded processors and digital signal processing (DSP).
" Experience programming in high-level languages such as C and C++.
" Experience developing hardware for automated test equipment (ATE).
" Experience managing distributed engineering teams, remote resources, and engineering contractors.
Education
Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) required.
Compensation and Benefits
The base salary range for this position is $155,500 $248,700 annually, depending on experience, qualifications, and location. The position is eligible for discretionary bonuses based on financial performance.
Benefits include medical, dental, and vision insurance; flexible spending accounts; retirement savings plans; life and disability insurance; paid vacation and holidays; and tuition assistance.
Welcome to ConsultNet, a premier national provider of technology talent and solutions. Our expertise spans across project services, contract-to-hire, direct search, and managed services onshore, nearshore, and hybrid. For over 25 years, we have connected thousands of consultants with meaningful roles through a personal, communication-driven approach, partnering with a diverse client base to build high-performing teams and create lasting impact. Our comprehensive service offerings cover a wide range of technology and engineering positions across key markets nationwide. Learn more at www.consultnet.com .
We champion equality and inclusivity, proudly supporting an Equal Opportunity Employer policy. We welcome applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, genetic information, disability, protected veteran status, or any other status protected by law.