Analog Layout Engineer - Senior Consultant

Hello, One of our direct client is urgently looking for Analog Engineer @ San Jose, CA Role- Analog Layout Engineer Location- San Jose, CA Contracting Position (six months with possible extension) Experience in- 16nm TSMC OR 14nm OR 22nm Intel The senior layout designer will be responsible for the layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.