Advanced ASIC Physical Design Lead

In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA).

Job Title: Advanced ASIC Physical Design Lead
Location: North Reading, MA
Duration: 12 months (Temp to Perm)
Payrate: $93 to $148 per hour

Job Description:
Client is seeking an experienced Physical Design Lead to join the Silicon Technology Engineering (STE) organization within the Digital ASIC Group. In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.

Responsibilities:

• Lead and mentor a team of physical design engineers across the full project lifecycle
• Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
• Develop and own chip floorplans, timing budgets, power estimates, and pin planning
• Partner with design teams to develop high-quality SDC constraints
• Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
• Support hands-on place-and-route (P&R) for critical and high-speed blocks
• Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
• Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
• Ensure robust signoff closure including DRC/LVS and EM/IR analysis
• Develop, enhance, and maintain physical design tool flows and automation

Must Have:

• 10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects
• Proven experience at advanced technology nodes (16nm and below)
• Deep expertise in RTL-to-GDSII flows and timing closure
• Strong understanding of STA, constraints development, and signoff methodologies
• Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
• Proficiency with industry-standard EDA tools (Cadence preferred)
• Strong scripting and automation skills using Tcl, Python, and/or Make
• Ability to lead technically, communicate clearly, and collaborate across disciplines
• BS or MS in Electrical Engineering (or equivalent practical experience)