(Mid/Sr/Staff/Princ) Layout Design Engineer (SerDes)

In this position you will play a key role in contributing to the development of advanced mixed-signal layout for low-power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low-power consumer SOCs.

You will join a highly collaborative team, and your success will have a significant impact on our products

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Layout design of advanced SERDES and other analog and mixed-signal macros in deep nanometer-level FinFET technologies
• Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed-signal transistor level layout
• DRC, LVS, and other physical verification tools

• Participate in post-layout circuit performance analysis
• Perform physical layout for custom structures in state-of-the-art nanometer-level CMOS technologies using Cadence tools.
• Assist in taking part in floor planning, custom layout, and verifying against design rules and schematics.
• Learn and ramp on new tools and methodologies
• Develop a realistic schedule for block-level layout including complete verifications

QUALIFICATIONS:

• At least 5-10+ years of hands-on layout design experience
• Experience in layout design of advanced SERDES.

• Good understanding of clock routing and shielding
• Good understanding of analog and mixed-signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
• Excellent team player